Abstract: A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.

Abstract: A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by depositing the copper in two stages with an optional dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brighteners and levelers. A first copper layer is plated at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio openings are covered with a substantial thickness of a uniform, high quality copper coating. During plating, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. Optionally, the brightener is replenished in these regions during a brief dwell period wherein the plating current is stopped.

Abstract: A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench.

Abstract: A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by performing the electrochemical deposition of copper in two deposition stages with an dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brightener and leveler. The first deposition is done at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio contact/via openings are covered with a substantial thickness of a uniform, high quality copper coating. During the deposition, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. The concentration of brighteners, is replenished in these regions by diffusion during a brief dwell period wherein the plating current is stopped.