Patents by Inventor WEN JYH LIN

WEN JYH LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240163010
    Abstract: Electronic device and operation method for an electronic device are provided. In the electronic device, a plurality of protocol data unit (PDU) blocks is generated to be transmitted on one or more lanes of a link. An advanced line encoding (ALE) frame is further generated based on an ALE scheme. The ALE scheme has an effective data rate larger than an effective data rate of 8b/10b coding scheme, and the ALE frame includes the plurality of PDU blocks, an error detection portion corresponding to the plurality of PDU blocks, and an error correction portion corresponding to the plurality of PDU blocks and the error detection portion. The ALE frame is transmitted on the one or more lanes of the link to another electronic device.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Applicant: SK hynix Inc.
    Inventor: WEN JYH LIN
  • Publication number: 20240118983
    Abstract: Method for facilitating testing for an interconnection protocol, a controller, and an electronic device are provided. The method is suitable for an electronic device capable of communicating with another electronic device. The method comprises the following steps. At a controller of the electronic device, a test mode request signal is received to enter a test mode in which data transmission is to be performed by using an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding. At the controller, a test data signal is generated to indicate a test pattern including an ordered set portion and a data pattern portion by using the advanced line encoding. The test data signal is transmitted according to the advanced line encoding through the electronic device to the other electronic device.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Applicant: SK hynix Inc.
    Inventor: WEN JYH LIN
  • Publication number: 20240121326
    Abstract: Electronic device and operation method for an electronic device are provided. In the electronic device, a specific number of protocol data units (PDUs) are received as a PDU block to be transmitted. The PDU block includes at least one PDU belonging to a control PDU category. A control block is generated according to the PDU block by reordering, wherein the control block includes a header being placed before all PDUs of the PDU block and indicating a control block category; in the control block, any PDU belonging to the control PDU category in the PDU block is placed after the header and before any PDU belonging to a data PDU category in the PDU block. The control block is transmitted through the electronic device to another electronic device according to an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Applicant: SK hynix Inc.
    Inventor: WEN JYH LIN
  • Publication number: 20240118974
    Abstract: A method for facilitating frame error handling and an electronic device are provided. The method is for use in an electronic device capable of communicating with another electronic device. The method comprises the following. In response to an error event in an advanced line encoding mode, closing a first burst transmission and opening a second burst transmission are performed, wherein the advanced line encoding mode indicates that the electronic device is capable of data transmission by using an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding. A lane alignment pattern is transmitted in the advanced line encoding mode from the electronic device to the other electronic device after the second burst transmission is opened. A negative acknowledgement control frame is transmitted in the advanced line encoding mode from the electronic device to the other electronic device after the lane alignment pattern is transmitted.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Applicant: SK hynix Inc.
    Inventor: WEN JYH LIN
  • Publication number: 20240121323
    Abstract: Method for control protocol frame transmission and electronic device are provided. The method comprises following operations. By the electronic device operating in an advanced line encoding mode and having a first burst from the electronic device to the other electronic device, the first burst is closed and a second burst is opened from the electronic device to the other electronic device for request frame transmission, wherein the electronic device operating in the advanced line encoding mode is configured to transmit data by using an advanced line encoding having an effective data rate larger than an effective data rate of 8b/10b encoding. By the electronic device, a request frame is transmitted in the second burst.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 11, 2024
    Applicant: SK hynix Inc.
    Inventors: LAN FENG WANG, WEN JYH LIN
  • Publication number: 20240120304
    Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.
    Type: Application
    Filed: November 24, 2022
    Publication date: April 11, 2024
    Applicant: Innolux Corporation
    Inventors: Tzu-Sheng Wu, Haw-Kuen Liu, Chung-Jyh Lin, Cheng-Chi Wang, Wen-Hsiang Liao, Te-Hsun Lin
  • Patent number: 11782636
    Abstract: A method for data processing of an interconnection protocol, a controller and a storage device, the method comprising in processing of frame sending by a first device to a second device: allocating a plurality of start-of-frame (SOF)-included protocol data units (PDUs) to a designated lane among a plurality of active lanes of the first device; and configuring a PDU distance among the plurality of start-of-frame (SOF)-included protocol data units to be greater than or equal to a product of a maximum bus width of a lane of the interconnection protocol and a quantity of the plurality of active lanes. Accordingly, the method can help greatly reduce the complexity of the hardware protocol engine implemented under the interconnection protocol, especially the complexity of the decoder in the data link layer receiver, thus reducing the difficulty of research and development, verification and maintenance.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 10, 2023
    Assignee: SK hynix Inc.
    Inventor: Wen Jyh Lin
  • Patent number: 11716169
    Abstract: A method for error handling of an interconnection protocol, a controller and a storage device are provided. The method for error handling of an interconnection protocol is for use in a first device that is linkable to a second device according to the interconnection protocol, the method comprising: during or after a power mode change of a link between the first device and the second device: a) triggering, by the first device, a first line reset signal to the second device; b) performing, by the first device, suppression of detected rate overlap errors; and c) stopping the suppression of detected rate overlap errors after the first device receives a second line reset signal from the second device.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: August 1, 2023
    Assignee: SK hynix Inc.
    Inventors: Cheng Wei Yu, Wen Jyh Lin, Lan Feng Wang
  • Patent number: 11687420
    Abstract: A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: June 27, 2023
    Assignee: SK hynix Inc.
    Inventors: Wen Jyh Lin, Yun Chih Huang, Fu Hsiung Lin
  • Publication number: 20230188256
    Abstract: A method for error handling of an interconnection protocol, a controller and a storage device are provided. The method for error handling of an interconnection protocol is for use in a first device that is linkable to a second device according to the interconnection protocol, the method comprising: during or after a power mode change of a link between the first device and the second device: a) triggering, by the first device, a first line reset signal to the second device; b) performing, by the first device, suppression of detected rate overlap errors; and c) stopping the suppression of detected rate overlap errors after the first device receives a second line reset signal from the second device.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 15, 2023
    Applicant: SK hynix Inc.
    Inventors: CHENG WEI YU, WEN JYH LIN, LAN FENG WANG
  • Publication number: 20230072876
    Abstract: A method for data processing of an interconnection protocol, a controller and a storage device, the method comprising in processing of frame sending by a first device to a second device: allocating a plurality of start-of-frame (SOF)-included protocol data units (PDUs) to a designated lane among a plurality of active lanes of the first device; and configuring a PDU distance among the plurality of start-of-frame (SOF)-included protocol data units to be greater than or equal to a product of a maximum bus width of a lane of the interconnection protocol and a quantity of the plurality of active lanes. Accordingly, the method can help greatly reduce the complexity of the hardware protocol engine implemented under the interconnection protocol, especially the complexity of the decoder in the data link layer receiver, thus reducing the difficulty of research and development, verification and maintenance.
    Type: Application
    Filed: December 22, 2021
    Publication date: March 9, 2023
    Applicant: SK hynix Inc.
    Inventor: WEN JYH LIN
  • Publication number: 20220276939
    Abstract: A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.
    Type: Application
    Filed: December 28, 2021
    Publication date: September 1, 2022
    Applicant: SK hynix Inc.
    Inventors: WEN JYH LIN, YUN CHIH HUANG, FU HSIUNG LIN