Patents by Inventor Wen-Kai Wan
Wen-Kai Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230154824Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm?1K?1and 1200 Wm?1K?1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Inventors: Ming-Tzong YANG, Hsien-Hsin LIN, Wen-Kai WAN, Chia-Che CHUNG, Chee-Wee LIU
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Patent number: 11587846Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1 and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor. A method of forming a semiconductor device includes providing a base substrate, forming a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1. The method further includes forming a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further includes removing the base substrate.Type: GrantFiled: December 24, 2020Date of Patent: February 21, 2023Assignees: MEDIATEK INC.Inventors: Ming-Tzong Yang, Hsien-Hsin Lin, Wen-Kai Wan, Chia-Che Chung, Chee-Wee Liu
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Publication number: 20220059429Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor.Type: ApplicationFiled: December 24, 2020Publication date: February 24, 2022Inventors: Ming-Tzong Yang, Hsien-Hsin Lin, Wen-Kai Wan, Chia-Che Chung, Chee-Wee Liu
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Patent number: 10741469Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.Type: GrantFiled: November 1, 2017Date of Patent: August 11, 2020Assignee: MEDIATEK INC.Inventors: Hsien-Hsin Lin, Ming-Tzong Yang, Wen-Kai Wan
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Publication number: 20180138104Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.Type: ApplicationFiled: November 1, 2017Publication date: May 17, 2018Inventors: Hsien-Hsin LIN, Ming-Tzong YANG, Wen-Kai WAN
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Patent number: 8450200Abstract: A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.Type: GrantFiled: December 20, 2010Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan, Jye-Yen Cheng
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Patent number: 8053894Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.Type: GrantFiled: August 26, 2005Date of Patent: November 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Kai Wan, Yih-Hsiung Lin, Ming-Ta Lei, Baw-Ching Perng, Cheng-Chung Lin, Chia-Hui Lin, Ai-Sen Liu
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Publication number: 20110092019Abstract: A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.Type: ApplicationFiled: December 20, 2010Publication date: April 21, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan, Jye-Yen Cheng
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Patent number: 7880303Abstract: An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.Type: GrantFiled: February 13, 2007Date of Patent: February 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan, Jye-Yen Cheng
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Patent number: 7791070Abstract: An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.Type: GrantFiled: November 2, 2005Date of Patent: September 7, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Kuan-Shou Chi, Wen-Kai Wan
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Patent number: 7777338Abstract: A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.Type: GrantFiled: September 13, 2004Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hsiang Yao, Tai-Chun Huang, Kuan-Shou Chi, Chih-Cherng Jeng, Ming-Shuoh Liang, Wen-Kai Wan, Chin-Chiu Hsia
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Patent number: 7741714Abstract: A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.Type: GrantFiled: November 2, 2004Date of Patent: June 22, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Wen-Kai Wan
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Publication number: 20080191352Abstract: An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.Type: ApplicationFiled: February 13, 2007Publication date: August 14, 2008Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan, Jye-Yen Cheng
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Patent number: 7291557Abstract: A method for forming an interconnection structure in an integrated circuit includes the following steps. A dielectric layer is formed on a semiconductor substrate. An opening is formed on the dielectric layer. A barrier layer is formed over inner walls of the opening and the dielectric layer. A conductive layer is deposited on the barrier layer and filling the opening. Then, a step of planarization is performed to form the interconnection structure, such that a peripheral edge of a top surface of the interconnection structure is no lower than a top surface of the barrier layer.Type: GrantFiled: September 13, 2004Date of Patent: November 6, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wen-Kai Wan, Chin-Chiu Hsia
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Patent number: 7271103Abstract: A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.Type: GrantFiled: October 17, 2003Date of Patent: September 18, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuei-Wu Huang, Ai-Sen Liu, Baw-Ching Perng, Ming-Ta Lei, Wen-Kai Wan, Cheng-Chung Lin, Yih-Shung Lin, Chia-Hui Lin
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Publication number: 20070096092Abstract: An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.Type: ApplicationFiled: November 2, 2005Publication date: May 3, 2007Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Kuan-Shou Chi, Wen-Kai Wan
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Publication number: 20060108696Abstract: A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.Type: ApplicationFiled: January 10, 2006Publication date: May 25, 2006Inventors: Chih-Hsiang Yao, Chin-Chiu Hsia, Wen-Kai Wan
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Patent number: 7042097Abstract: A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.Type: GrantFiled: June 6, 2003Date of Patent: May 9, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Hsiang Yao, Chin-Chiu Hsia, Wen-Kai Wan
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Publication number: 20060091536Abstract: A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.Type: ApplicationFiled: November 2, 2004Publication date: May 4, 2006Inventors: Tai-Chun Huang, Chih-Hsiang Yao, Wen-Kai Wan
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Publication number: 20060057841Abstract: A method for forming an interconnection structure in an integrated circuit includes the following steps. A dielectric layer is formed on a semiconductor substrate. An opening is formed on the dielectric layer. A barrier layer is formed over inner walls of the opening and the dielectric layer. A conductive layer is deposited on the barrier layer and filling the opening. Then, a step of planarization is performed to form the interconnection structure, such that a peripheral edge of a top surface of the interconnection structure is no lower than a top surface of the barrier layer.Type: ApplicationFiled: September 13, 2004Publication date: March 16, 2006Inventors: Wen-Kai Wan, Chin-Chiu Hsia