Patents by Inventor Wen Ke
Wen Ke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12279536Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.Type: GrantFiled: March 19, 2024Date of Patent: April 15, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
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Publication number: 20250089448Abstract: An organic light-emitting diode display device includes a first light-emitting layer, a first anode, a first reflective pattern, and a dielectric material. The first light-emitting layer, the first anode, and the first reflective pattern are located in a first sub-pixel region. The first anode is disposed under the first light-emitting layer in a vertical direction, and the first reflective pattern is disposed under the first anode in the vertical direction. The dielectric material is partly disposed between the first anode and the first reflective pattern, and the first reflective pattern is electrically connected with the first anode.Type: ApplicationFiled: October 19, 2023Publication date: March 13, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yen-Tsai Yi, Wei-Chuan Tsai, Jin-Yan Chiou, Hsiang-Wen Ke
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Publication number: 20250081568Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.Type: ApplicationFiled: November 17, 2024Publication date: March 6, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Yen-Tsai Yi, Hsiang-Wen Ke
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Publication number: 20250028639Abstract: Various embodiments of the teachings herein include a method for graph data caching. An example method includes: receiving a first semantic query on graph data; extracting, from the first semantic query, each first value of at least one semantic element; matching the first semantic query with at least one second semantic query stored in the cache based on each first value of the at least one semantic element; if the first semantic query has a match, achieving graph data linked with the at least one matched second semantic query from the cache, otherwise, achieving graph data from a database; and storing, in the cache, the first semantic query and the achieved graph data, wherein the first semantic query is linked with the achieved graph data.Type: ApplicationFiled: August 30, 2021Publication date: January 23, 2025Applicant: Siemens AktiengesellschaftInventor: Wen Ke Wang
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Patent number: 12183801Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.Type: GrantFiled: October 26, 2021Date of Patent: December 31, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Yen-Tsai Yi, Hsiang-Wen Ke
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Publication number: 20240397832Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunneling junction (MTJ) on a substrate, a first top electrode on the MTJ, a second top electrode on and directly contacting the first top electrode, and a spacer adjacent to the MTJ. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yen-Tsai Yi, Wei-Chuan Tsai, Jin-Yan Chiou, Hsiang-Wen Ke
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Patent number: 12089504Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.Type: GrantFiled: June 29, 2021Date of Patent: September 10, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Tsai Yi, Wei-Chuan Tsai, Jin-Yan Chiou, Hsiang-Wen Ke
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Publication number: 20240237550Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.Type: ApplicationFiled: March 21, 2024Publication date: July 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
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Publication number: 20240237549Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.Type: ApplicationFiled: March 19, 2024Publication date: July 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
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Publication number: 20240143045Abstract: An independent graphics card system comprises an expansion motherboard, a system power supply, at least one expansion graphics card and a fan assembly. The system power supply is electrically connected to the expansion motherboard. The at least one expansion graphics card is plugged into the expansion motherboard through an adapter card. The at least one expansion graphics card is parallel with the expansion motherboard. The fan assembly dissipates heat of the at least one expansion graphics card.Type: ApplicationFiled: October 18, 2023Publication date: May 2, 2024Inventors: SUNG-HSIEN LEE, WEN-KE WU, ZHI-FENG WEI, BIAO ZENG
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Patent number: 11968906Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.Type: GrantFiled: May 25, 2020Date of Patent: April 23, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Hsin-Fu Huang, Yen-Tsai Yi, Hsiang-Wen Ke
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Patent number: 11940140Abstract: Disclosed herein is a light transmissive fiber integrated knit textile for use on consumer electronic products. The knit textile is depicted to be constructed with light transmissive fibers integration through a weave-in/inlay knit technique with a flat-bed knitting construction. The light transmissive knitted textile is also tethered to a portable electronic device, allowing for the light transmitting fibers knitted into the fabric to define a lighting display on said fabric.Type: GrantFiled: December 8, 2022Date of Patent: March 26, 2024Assignees: AUSSCO HONG KONG LTD, INDHOUSE LIMITEDInventors: Christine Lew, Jackson Chow, Tiffany Williams, Vince Ho, Wen Ke Xi
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Publication number: 20230387280Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a titanium nitride (TiN) layer on the p-type semiconductor layer as a nitrogen to titanium (N/Ti) ratio of the TiN layer is greater than 1, forming a passivation layer on the TiN layer and the barrier layer, removing the passivation layer to form an opening, forming a gate electrode in the opening, and then forming a source electrode and a drain electrode adjacent to two sides of the gate electrode on the buffer layer.Type: ApplicationFiled: June 28, 2022Publication date: November 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yen-Tsai Yi, Wei-Chuan Tsai, Jin-Yan Chiou, Hsiang-Wen Ke
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Publication number: 20230284955Abstract: Disclosed herein is a flat-bed knit-based electrode structure that has non-electrically conductive regions and electrically conductive regions. The non-electrically conductive regions are formed from a knitted textile including non-conductive yarns, and the electrically conductive regions are formed from a knitted textile having electrically conductive yarn. The electrically conductive regions are knitted using a conductive hybrid yarn containing a non-conductive multifilament with polymer and coated with carbon. The electrically conductive regions can transmit electrical data or power signals along the knitted textile via the conductive yarn. A connector links the conductive region to a wireless device that can output heart rate data of the user.Type: ApplicationFiled: March 14, 2023Publication date: September 14, 2023Inventors: Tiffany Keesha Agathina WILLIAMS, Jackson Hoi Fung CHOW, Wen Ke XI
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Publication number: 20230184423Abstract: Disclosed herein is a light transmissive fiber integrated knit textile for use on consumer electronic products. The knit textile is depicted to be constructed with light transmissive fibers integration through a weave-in/inlay knit technique with a flat-bed knitting construction. The light transmissive knitted textile is also tethered to a portable electronic device, allowing for the light transmitting fibers knitted into the fabric to define a lighting display on said fabric.Type: ApplicationFiled: December 8, 2022Publication date: June 15, 2023Inventors: Christine LEW, Jackson CHOW, Tiffany WILLIAMS, Vince HO, Wen Ke Xi
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Publication number: 20230125856Abstract: A method for fabricating a semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a barrier layer in the trench, forming a nucleation layer on the barrier layer, performing an anneal process to form a silicide layer, forming a bulk layer on the silicide layer, and forming a magnetic tunneling junction (MTJ) on the bulk layer.Type: ApplicationFiled: November 23, 2021Publication date: April 27, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsiang-Wen Ke, Wei-Chuan Tsai, Yen-Tsai Yi, Jin-Yan Chiou
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Publication number: 20230094638Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a source/drain region adjacent to two sides of the gate structure, forming an epitaxial layer on the source/drain region, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer to expose the epitaxial layer, forming a low stress metal layer in the contact hole, forming a barrier layer on the low stress metal layer, and forming an anneal process to form a first silicide layer and a second silicide layer.Type: ApplicationFiled: October 26, 2021Publication date: March 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Yen-Tsai Yi, Hsiang-Wen Ke
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Publication number: 20220384710Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.Type: ApplicationFiled: June 29, 2021Publication date: December 1, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yen-Tsai Yi, Wei-Chuan Tsai, Jin-Yan Chiou, Hsiang-Wen Ke
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Patent number: 11509873Abstract: A light source generating device, a projection apparatus and a light source generation method are provided. The light source generating device includes a first light source, an auxiliary light source, a control device, a driver and a current command generator. The first light source generates a first light beam. The auxiliary light source generates an auxiliary light beam corresponding to the first light beam. The control device generates a first driving signal to drive the first light source. The driver generates an auxiliary driving signal to drive the auxiliary light source according to the gate control signal and a current command. The current command generator receives an indication signal, and generates the current command according to the indication signal, wherein the indication signal corresponds to a driving current of the first light source. The invention has an effect of enhancing brightness/chrominance.Type: GrantFiled: January 10, 2019Date of Patent: November 22, 2022Assignee: Coretronic CorporationInventors: Chi-Wen Ke, Hung-Wei Lin, Chun-Yi Lee
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Patent number: 11450564Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.Type: GrantFiled: September 12, 2019Date of Patent: September 20, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Yen-Tsai Yi, Li-Han Chen, Hsiang-Wen Ke