Abstract: A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.

Abstract: A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.

Abstract: A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.

Abstract: A voltage down converter for programming a one-time-programmable (OTP) memory comprising is disclosed, the voltage down converter comprises a bonding pad for coupling to a programming power supply, and at least one forward biased diode coupled between the bonding pad and the OTP memory, wherein a programming voltage received by the OTP memory is lowered from the programming power supply by the voltage drop across the forward biased diode.

Abstract: A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.

Abstract: A sense amplifier includes a first transistor coupled between a match line of a CAM array and a VDD supply terminal. The match line is pre-charged through the first transistor to a voltage equal to a reference voltage minus the first transistor threshold voltage, VT1. The match line is coupled to the source of a second transistor, which has a threshold voltage VT2, wherein VT2>VT1. A dummy line of the CAM array, which is coupled to the gate of the second transistor, is pre-charged to the reference voltage. A storage node, which is coupled to the drain of the second transistor, is pre-charged to the VDD supply voltage. A non-match condition causes the voltage on the match line to be pulled down. When the voltage on the dummy line exceeds the voltage on the match line by VT2, the second transistor turns on, thereby pulling down the storage node.

Abstract: A bias control circuit for controlling the bias current in a sense amplifier circuit. The bias control circuit maintains a substantially constant bias current when the V.sub.CC supply voltage decreases, thereby maintaining the operating speed of the sense amplifier circuit at a predetermined level. The bias control circuit also increases the bias current as the temperature of the sense amplifier circuit increases, thereby maintaining the operating speed of the sense amplifier circuit at the predetermined level. Furthermore, the bias circuit controls the logic low voltage provided by the sense amplifier circuit to be less than a predetermined threshold value, even as the V.sub.CC supply voltage increases.