Patents by Inventor Wen-Kuei Huang
Wen-Kuei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9263095Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.Type: GrantFiled: July 29, 2013Date of Patent: February 16, 2016Assignee: Micron Technology, Inc.Inventors: Kunal Parekh, David Hwang, Wen Kuei Huang, Kuo Chen Wang, Ching Kai Lin
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Publication number: 20130314967Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.Type: ApplicationFiled: July 29, 2013Publication date: November 28, 2013Applicant: Micron Technology, Inc.Inventors: Kunal Parekh, David Hwang, Wen Kuei Huang, Kuo Chen Wang, Ching Kai Lin
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Patent number: 8547729Abstract: A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size.Type: GrantFiled: August 14, 2008Date of Patent: October 1, 2013Assignee: Nanya Technology CorporationInventor: Wen-Kuei Huang
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Patent number: 8497541Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.Type: GrantFiled: March 10, 2010Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Kunal Parekh, David Hwang, Wen Kuei Huang, Kuo Chen Wang, Ching Kai Lin
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Patent number: 8188552Abstract: A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape.Type: GrantFiled: July 30, 2010Date of Patent: May 29, 2012Assignee: Nanya Technology Corp.Inventor: Wen-Kuei Huang
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Publication number: 20110220980Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Applicant: Micron Technology, Inc.Inventors: Kunal Parekh, David Hwang, Wen Kuei Huang, Kuo Chen Wang, Ching Kai Lin
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Publication number: 20100295106Abstract: A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape.Type: ApplicationFiled: July 30, 2010Publication date: November 25, 2010Inventor: Wen-Kuei Huang
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Patent number: 7795620Abstract: A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape.Type: GrantFiled: December 18, 2008Date of Patent: September 14, 2010Assignee: Nanya Technology Corp.Inventor: Wen-Kuei Huang
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Patent number: 7763924Abstract: A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor.Type: GrantFiled: October 2, 2008Date of Patent: July 27, 2010Assignee: Nanya Technology Corp.Inventor: Wen-Kuei Huang
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Publication number: 20100052029Abstract: A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape.Type: ApplicationFiled: December 18, 2008Publication date: March 4, 2010Inventor: Wen-Kuei Huang
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Publication number: 20100019301Abstract: A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor.Type: ApplicationFiled: October 2, 2008Publication date: January 28, 2010Inventor: Wen-Kuei Huang
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Publication number: 20090257262Abstract: A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size.Type: ApplicationFiled: August 14, 2008Publication date: October 15, 2009Applicant: NANYA TECHNOLOGY CORPORATIONInventor: Wen-Kuei Huang
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Patent number: 7495253Abstract: An organic thin-film transistor and a method for manufacturing the same are described. The method forms a gate layer on a substrate, an insulator layer on the substrate, forming a semiconductor layer on the insulator layer, and a strip for defining a channel length on the semiconductor layer. An electrode layer is screen printed on the semiconductor layer, and a passivation layer is coated on the electrode layer. The organic thin-film transistor manufactured by the method of the invention has a substrate, a gate layer formed on the substrate, an insulator layer formed on the substrate, a semiconductor layer formed on the insulator layer, a strip for defining a channel length formed on the semiconductor layer, an electrode layer screen-printed on the semiconductor layer, and a passivation layer coated on the electrode layer. Thereby, an organic thin-film transistor with a top-contact/bottom-gate structure is obtained.Type: GrantFiled: July 27, 2007Date of Patent: February 24, 2009Assignee: Industrial Technology Research InstituteInventors: Liang-Ying Huang, Jia-Chong Ho, Cheng-Chung Lee, Tarng-Shiang Hu, Wen-Kuei Huang, Wei-Ling Lin, Cheng-Chung Hsieh
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Publication number: 20080035918Abstract: An organic thin-film transistor and a method for manufacturing the same are described. The method forms a gate layer on a substrate, an insulator layer on the substrate, forming a semiconductor layer on the insulator layer, and a strip for defining a channel length on the semiconductor layer. An electrode layer is screen printed on the semiconductor layer, and a passivation layer is coated on the electrode layer. The organic thin-film transistor manufactured by the method of the invention has a substrate, a gate layer formed on the substrate, an insulator layer formed on the substrate, a semiconductor layer formed on the insulator layer, a strip for defining a channel length formed on the semiconductor layer, an electrode layer screen-printed on the semiconductor layer, and a passivation layer coated on the electrode layer. Thereby, an organic thin-film transistor with a top-contact/bottom-gate structure is obtained.Type: ApplicationFiled: July 27, 2007Publication date: February 14, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Liang-Ying Huang, Jia-Chong Ho, Cheng-Chung Lee, Tarng-Shiang Hu, Wen-Kuei Huang, Wei-Ling Lin, Cheng-Chung Hsieh
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Publication number: 20080007836Abstract: A microlens module applicable in an optoelectronic device and a method for fabricating the microlens module are proposed, by which an array of microlenses can be fabricated on an optoelectronic device. The present invention is characterized that a self-assembling monolayer is imprinted onto a substrate using an imprinting technique, so as to define a microlens predetermining distribution region and a peripheral region. Then, a solution with a high light transmittance is jetted on the microlens predetermining distribution region using an ink-jet printing technique, so as to form microlenses. In comparison to prior-art techniques, as the method for fabricating the microlens module on the optoelectronic device does not require complicated and expensive techniques, the present invention is simple in fabrication and cost-effective.Type: ApplicationFiled: November 29, 2006Publication date: January 10, 2008Inventors: Jhih-Ping Lu, Wen-Kuei Huang, Fang-Chung Chen, Yuh-Zheng Lee, Chao-Kai Cheng
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Patent number: 7304424Abstract: An anode plate for a field emission display device (FED) is disclosed, which has a substrate; an anode conductive layer formed on the substrate; at least one interspacing conductive band having a plurality of internal gaps for connecting the anode conductive layer and external cable lines, wherein the interspacing conductive band covers a part of the anode conductive layer; and a fluorescent layer located on the anode conductive layer, to serve as a source of luminescence for a field emission display device. The field emission display device includes the anode plate aforesaid as is also disclosed.Type: GrantFiled: January 21, 2004Date of Patent: December 4, 2007Assignee: Industrial Technology Research InstituteInventors: Ying-Hsien Cheng, Cheng-Chung Lee, Wen-Kuei Huang, Wei-Yi Lin, Jia-Chong Ho, Yu-Yang Chang, Ming-Chun Hsiao, Yun-Chiao Hsiao
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Publication number: 20070217019Abstract: A process of fabricating a microlens array is provided. A self-assembled monolayer is formed on a substrate to form a hydrophilic region and a hydrophobic region. A liquid material is coated on the substrate so that a plurality of liquid microlenses is condensed on the hydrophilic region. The liquid microlenses are cured to form a plurality of microlenses.Type: ApplicationFiled: March 16, 2006Publication date: September 20, 2007Inventors: Wen-Kuei Huang, Chu-Jung Ko, Fang-Chung Chen
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Patent number: 7264989Abstract: An organic thin-film transistor and a method for manufacturing the same are described. The method forms a gate layer on a substrate, an insulator layer on the substrate, forming a semiconductor layer on the insulator layer, and a strip for defining a channel length on the semiconductor layer. An electrode layer is screen printed on the semiconductor layer, and a passivation layer is coated on the electrode layer. The organic thin-film transistor manufactured by the method of the invention has a substrate, a gate layer formed on the substrate, an insulator layer formed on the substrate, a semiconductor layer formed on the insulator layer, a strip for defining a channel length formed on the semiconductor layer, an electrode layer screen-printed on the semiconductor layer, and a passivation layer coated on the electrode layer. Thereby, an organic thin-film transistor with a top-contact/bottom-gate structure is obtained.Type: GrantFiled: May 7, 2004Date of Patent: September 4, 2007Assignee: Industrial Technology Research InstituteInventors: Liang-Ying Huang, Jia-Chong Ho, Cheng-Chung Lee, Tarng-Shiang Hu, Wen-Kuei Huang, Wei-Ling Lin, Cheng-Chung Hsieh
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Publication number: 20070159059Abstract: An anode plate for a field emission display device (FED) is disclosed, which has a substrate; an anode conductive layer formed on the substrate; at least one interspacing conductive band having a plurality of internal gaps for connecting the anode conductive layer and external cable lines, wherein the interspacing conductive band covers a part of the anode conductive layer; and a fluorescent layer located on the anode conductive layer, to serve as a source of luminescence for a field emission display device. The field emission display device includes the anode plate aforesaid as is also disclosed.Type: ApplicationFiled: February 20, 2007Publication date: July 12, 2007Applicant: Industrial Technology Research InstituteInventors: Ying-Hsien Chen, Cheng-Chung Lee, Wen-Kuei Huang, Wei-Yi Lin, Jia-Chong Ho, Yu-Yang Chang, Ming-Chun Hsiao, Yun-Chiao Hsiao
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Patent number: 7125742Abstract: The present invention discloses a multi-passivation layer structure for organic thin-film transistors and a method for fabricating the same by spin coating, inject printing, screen printing and micro-contact on organic thin-film transistors. The multi-passivation layer structure for organic thin-film transistors, comprising: a substrate; a gate layer formed on the substrate; an insulator layer formed on the substrate and the gate layer; an electrode layer formed on the insulator layer; a semiconductor layer formed on the insulator layer and the electrode layer; and a passivation layer formed on the semiconductor layer and the electrode layer, thereby forming a multi-passivation layer structure for organic thin-film transistors.Type: GrantFiled: June 9, 2004Date of Patent: October 24, 2006Assignee: Industrial Technology Research InstituteInventors: Cheng-Chung Hsieh, Jia-Chong Ho, Tarng-Shiang Hu, Cheng-Chung Lee, Liang-Ying Huang, Wei-Ling Lin, Wen-Kuei Huang