Abstract: A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin. A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.

Abstract: A signoff process includes: accessing circuit information of a circuit; performing, using an analysis and optimization engine, power analysis and optimization on the circuit to generate an optimized circuit, the power analysis and optimization being performed using an input pattern; performing, using a simulator, a simulation on at least a portion of an optimized circuit, the simulation being performed using the input pattern used in the power analysis and optimization; and outputting a simulation result to the analysis and optimization engine; wherein the analysis and optimization engine and the simulator are integrated.

Abstract: A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin. A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.

Abstract: A signoff process includes: accessing circuit information of a circuit; performing, using an analysis and optimization engine, power analysis and optimization on the circuit to generate an optimized circuit, the power analysis and optimization being performed using an input pattern; performing, using a simulator, a simulation on at least a portion of an optimized circuit, the simulation being performed using the same input pattern; and outputting a simulation result to the analysis and optimization engine; wherein the analysis and optimization engine and the simulator are integrated.