Patents by Inventor Wen Lee

Wen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250064964
    Abstract: The present invention provides antibody drug conjugates, wherein an antibody or antibody fragment that specifically binds to human cKIT is linked to a drug moiety, optionally through a linker. The present invention further provides pharmaceutical compositions comprising the antibody drug conjugates; and methods of making and using such pharmaceutical compositions for ablating hematopoetic stem cells in a patient in need thereof.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 27, 2025
    Inventors: Anthony Edward Boitano, Matthew Burger, Susan E. Cellitti, Michael P. Cooke, Catrin Finner, Bernhard Hubert Geierstanger, Yunho Jin, Si Tuen Lee-Hoeflich, HongNgoc Thi Pham, Siew Ho Schleyer, Kathrin Tissot, Tetsuo Uno, Ben Wen
  • Publication number: 20250072143
    Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 27, 2025
    Inventors: Li-Wen HUANG, Chung-Liang CHENG, Ping-Hao LIN, Kuo-Cheng LEE
  • Publication number: 20250072080
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer on the gate structure, forming a patterned mask on the gate structure and one side of the gate structure, removing the first spacer on another side of the gate structure, and then forming a source/drain region adjacent to two sides of the gate structure.
    Type: Application
    Filed: September 25, 2023
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Yih Chen, Yi-Wen Chen, Chia-Chen Sun, Wei-Chung Sun, Wan-Ching Lee
  • Patent number: 12238395
    Abstract: A playback application is configured to dynamically generate topology for an interactive media title. The playback application obtains an initial topology and also collects various data associated with a user interacting with the feature. The playback application then modifies the initial topology, based on the collected data, to generate a dynamic topology tailored to the user. The dynamic topology describes the set of choices available to the user during playback as well as which options can be selected by the user when making a given choice. In addition, the playback application also selectively buffers different portions of the interactive media title, based on the collected data, in anticipation of the user selecting particular options for available choices.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: February 25, 2025
    Assignee: NETFLIX, INC.
    Inventors: Maxine Cheung, Mark Watson, Carla Christine Fisher, Kevin Pei-Wen Lee, Yves Raimond
  • Publication number: 20250063791
    Abstract: Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 20, 2025
    Inventors: Tsung-Lin Lee, Wei-Yang Lee, Ming-Chang Wen, Chien-Tai Chan, Chih Chieh Yeh, Da-Wen Lin
  • Publication number: 20250063720
    Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yen-Chieh Huang, Wei-Gang Chiu, Kai-Wen Cheng, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250062153
    Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Inventors: Chien-Fa LEE, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO, Jian-Hung CHEN, M.C. LIN, C.C. CHIEN, Hsuan LEE, Boris HUANG
  • Patent number: 12220550
    Abstract: Provided is a device for transdermal delivery of drugs. The device includes a separable substrate and is loaded with dual drugs based on an interpenetrating polymer network hydrogel. Also provided are methods of making and using the transdermal delivery device.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 11, 2025
    Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATION
    Inventors: Yu-Shuan Chen, Hsieh-Chih Tsai, Chang-Yi Lee, Haile Fentahun Darge, Shinn-Zong Lin, Tzyy-Wen Chiou, Chia-Yu Chang
  • Patent number: 12224324
    Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Huang, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250043075
    Abstract: A modified polyphenylene ether resin having a structure represented by [Formula 1] is provided.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 6, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Cheng-Chung Lee, Chen Hua Wu, Jung Kai Chang, Yun-Chia Tsai, Hung-Wen Hsu
  • Publication number: 20250045141
    Abstract: A method, computer program product, and computing system for processing a plurality of log files from one or more storage systems. A log pattern concerning at least two or more log files is identified by processing each log file from the plurality of log files using one or more processing threads. A potential overlogging issue associated with the log pattern is identified.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Inventors: Jing Chen, Michael Lee Burriss, Wen Jiang, Rong Yang
  • Publication number: 20250043176
    Abstract: An organic electroluminescent material is used for a sensitizer layer of an organic light-emitting diode. The organic electroluminescent material includes a structure of the following General Formula (1): A is selected from the group consisting of General Formula (2), a carbazole group, and a substituted benzimidazole group. The present invention also discloses an organic light-emitting diode which has a sensitizer layer. The sensitizer layer includes a structure of General Formula (1).
    Type: Application
    Filed: August 2, 2024
    Publication date: February 6, 2025
    Inventors: Tien-Lung CHIU, Man-Kit LEUNG, Chia-Hsun CHEN, Chen-Jun CHU, Chi-Chi CHANG, Yi-Ru HAUNG, Jiun-Haw LEE, Lian-Chun HUANG, Zi-Wen SU, Yuan-Zhen ZUANG, Jing-Xiang HUANG
  • Publication number: 20250041222
    Abstract: The present disclosure relates to a copolymer and a polymersome for targeted delivery of biomolecules to a living organism. The exemplary copolymer comprises an initiator block, a propagator block, and a linkage connecting the initiator block and the propagator block. The initiator block comprises a glycan head configured to provide a targeted delivery, and the propagator block comprises a functional moiety configured to provide desired properties for the polymersome.
    Type: Application
    Filed: April 8, 2024
    Publication date: February 6, 2025
    Inventors: Chi-Huey Wong, Jeng Shin LEE, Chen-Yo FAN, Szu-Wen WANG
  • Patent number: 12216142
    Abstract: Current sensing resistors and a method of manufacturing the same are disclosed in the present invention. A composite material is firstly provided in the method. Then, a first portion of an alloy substrate of the composite material is removed along a first direction to form a plurality of first trenches. Next, a second portion of the alloy substrate of the composite material is removed along a second direction to form a plurality of second trenches, and a third portion of the alloy substrate of the composite material is further removed along the first direction to form the current sensing resistors. The current sensing resistors with small dimensions and an extremely low temperature coefficient of resistance can be produced rapidly by the method of the present invention.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: February 4, 2025
    Assignee: YAGEO CORPORATION
    Inventors: Shen-Li Hsiao, Hwan-Wen Lee
  • Patent number: 12218240
    Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium con
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
  • Patent number: 12218159
    Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Lei Chen, Clark Lee, Wen-Sheng Wang, Chien-Li Kuo
  • Patent number: 12211836
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
  • Patent number: 12211919
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Chih-Han Lin, Hsiao Wen Lee
  • Patent number: 12211737
    Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a conductive structure on a substrate. A removal process is performed to remove a portion of the dielectric layer to expose a portion of the conductive structure. The substrate is transported into a cleaning chamber having a wafer chuck below a bell jar structure. A cleaning process is performed to clean the exposed portion of the conductive structure by turning on a noble gas source to introduce a noble gas within the cleaning chamber, turning on an oxygen gas source to introduce oxygen within the cleaning chamber, applying a first bias to a plasma coil to form a plasma gas, and applying a second bias to the wafer chuck. The substrate is removed from the cleaning chamber. A conductive layer is formed over the dielectric layer and coupled to the conductive structure.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Liang Lin, Chia-Wen Zhong, Yao-Wen Chang, Min-Chang Ching, Kuo-Liang Lu, Cheng-Yuan Tsai, Ru-Liang Lee
  • Patent number: D1063925
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: February 25, 2025
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Yang Chien, Hao-Jen Fang, Wei-Yi Chang, Chun-Chieh Chen, Chen-Cheng Wang, Chih-Wen Chiang, Sheng-Hung Lee