Abstract: Disclosed is a vacuum chuck and a method for securing a warped semiconductor substrate during a semiconductor manufacturing process so as to improve its flatness during a semiconductor manufacturing process. For example, a semiconductor manufacturing system includes: a vacuum chuck configured to hold a substrate, wherein the vacuum chuck comprises, a plurality of vacuum grooves located on a top surface of the vacuum chuck, wherein the top surface is configured to face the substrate; and a plurality of flexible seal rings disposed on the vacuum chuck and extending outwardly from the top surface, wherein the plurality of flexible seal rings are configured to directly contact a bottom surface of the substrate and in adjacent to the plurality of vacuum grooves so as to form a vacuum seal between the substrate and the vacuum chuck, and wherein each of the plurality of flexible seal rings has a zigzag cross section.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

Abstract: Provided is a process for manufacturing a graphene material, the process comprising (a) injecting a rust stock into a first end of a continuous reactor having a toroidal vortex flow, wherein the first stock comprises graphite and a non-oxidizing liquid (or, alternatively, graphite, an acid, and an optional oxidizer) and the continuous flow reactor is configured to produce the toroidal vortex flow, enabling the formation of a reaction product suspension or slurry at the second end, downstream from the first end, of the continuous reactor; and (b) introducing the reaction product suspension/slurry from the second end back to enter the continuous reactor at or near the first end, allowing the reaction product suspension/slurry to form a toroidal vortex flow and move down to or near the second end to produce a graphene suspension or graphene oxide slurry. The process may further comprise repeating step (b) for at least one time.

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. In one example, a device includes a substrate, pixel-defining layer (PDL) structures disposed over the substrate and defining sub-pixels of the device, and a plurality of overhang structures. The first sub-pixel includes a first anode, OLED material, a first cathode, and a first encapsulation layer having a gap defined by a first portion of the first encapsulation layer disposed over the first cathode, a second portion of the first encapsulation layer disposed over a sidewall of the body structure, and a third portion of the first encapsulation layer under an underside surface of the top extension of the top structure, the first portion of the first encapsulation layer contacting the third portion of the first encapsulation layer.

Abstract: Described is a shoe, in particular an athletic shoe. The shoe can include a sole and a shoe upper. The shoe upper can include (a.) a lateral portion; (b.) a medial portion; and (c.) intermediate portion between the lateral portion and the medial portion. The intermediate portion can include a portion uncoated by a first coating portion on the lateral portion and a second coating portion on the medial portion.

Abstract: A micro-light-emitting diode (microLED) display panel includes a substrate; a plurality of microLEDs disposed and arranged in rows and columns on the substrate; a driver disposed on the substrate; a plurality of first blocking walls respectively disposed between rows of the microLEDs; and a plurality of second blocking walls respectively disposed between the microLEDs of the same row.

Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.

Abstract: A location-related topic discussion system, an operating method, and a computer-readable recording medium are provided. The system includes a server having a topic-discussion database. In the server, the topic-discussion database is queried for obtaining one or more location-related discussion topics within a geographic range according to location information transmitted by a user device. The server then provides one or more location-related discussion-topic-category linking icons to the user device, and the one or more icons can be marked on a graphical user interface initiated by the user device. When a user selects one of location-related discussion-topic-category links, the server accordingly provides contents on a first layer topic-discussion page to be displayed by the user device. The first layer topic-discussion page includes multiple popularity-sorted topic-discussion areas and location-related discussion topic categories in accordance with personal preference of the user.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; depositing a mask layer over the substrate; forming a mandrel pattern over the mask layer; forming a spacer pattern around the mandrel pattern; removing the mandrel pattern; and applying at least one directional etching operation along a first direction to etch two opposing ends of the spacer pattern and form a first spacer feature and a second spacer feature apart from each other.

Abstract: A semiconductor device includes a first type of light sensing units, where each instance of the first type of light sensing units is operable to receive a first amount of radiation; and a second type of light sensing units, where each instance of the second type of light sensing units is operable to receive a second amount of radiation, and the second type of light sensing units is arranged in an array with the first type of light sensing units to form a pixel sensor. The first amount of radiation is smaller than the second amount of radiation, and at least a first instance of the first type of light sensing units is adjacent to a second instance first type of light sensing unit.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a semiconductor fin structure including first semiconductor layers and second semiconductor layers alternatingly stacked, laterally recessing the first semiconductor layers of the semiconductor fin structure to form first notches in the first semiconductor layers, forming first passivation layers on first sidewalls of the first semiconductor layers exposed from the first notches, and forming first inner spacer layers in the first notches.

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.

Abstract: Disclosed is an electronic device including a display module, a touch light-emitting module, and a processing unit. The touch light-emitting module includes a light-transmitting unit, a touch unit, and a light-emitting unit. The touch unit is disposed under the light-transmitting unit and is adapted to generate a touch signal based on touch of the user on the light-transmitting unit. The light-emitting unit is disposed on the touch unit. The light-emitting unit is adapted to provide an illumination beam to the light-transmitting unit according to an illumination signal. The processing unit is electrically connected to the display module and the touch light-emitting module. When the electronic device is switched to a touch mode, the processing unit disables the light-10 emitting unit. When the electronic device is switched to a content input mode, the processing unit enables the light-emitting unit to provide the illumination beam to the light-transmitting unit.

Abstract: Provided is a method of accurate and sensitive characterization and prognosis of prostate cancer in a subject. The method includes obtaining a biological sample from the subject and determining the level of identified biomarkers.

Abstract: A roller module includes a scroll wheel, a magnetization member, a swinging element and a pole-reversible magnetic element. The magnetization member is synchronously rotated with the scroll wheel. The swinging element includes a pivotal part, a first magnetic element and a second magnetic element. The first magnetic element and the second magnetic element are movable by using the pivotal part as a rotation center. The pole-reversible magnetic element and the first magnetic element interact with each other. Consequently, the second magnetic element is close to or away from the magnetization member.

Abstract: A collaboration system and a collaboration method are provided. The collaboration system includes a first display device and a second display device. The first display device includes a first screen. The first screen displays a first display interface. The first display interface has a first display window and a first function key. The first display window displays a first frame. The second display device includes a second display screen. The second display screen displays a second display interface. The second display interface has a second display window. The second display window displays a second frame. When the first function key is turned on, the first frame moves along with the second frame. When the first function key is turned off, the first frame does not follow the movement of the second frame.

Abstract: A semiconductor die and the method of forming the same are provided. The semiconductor die includes a first interconnect structure, a second interconnect structure including a conductive feature, and a device layer between the first interconnect structure and the second interconnect structure. The device layer includes a semiconductor fin, a first gate structure on the semiconductor fin, a source/drain region adjacent the first gate structure, and a shared contact extending through the semiconductor fin to be electrically connected to the source/drain region and the first gate structure. The conductive feature contacts the shared contact.

Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.