Patents by Inventor Wen-Li Chiu

Wen-Li Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250062158
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base and a fin over the base. The method includes forming a first gate stack wrapped around the fin. The method includes forming a first gate spacer over a first sidewall of the first gate stack. The method includes partially removing the fin, which is not covered by the first gate stack and the first gate spacer. The method includes removing a first upper portion of the first gate stack to expose a second upper portion of the first gate spacer. The method includes removing the second upper portion of the first gate spacer. The method includes removing a first lower portion of the first gate stack and the fin originally wrapped by the first gate stack. The method includes forming a dielectric channel-cut structure in the trench.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Li CHIU, Chia-Hao Kuo, Fu-Hsiang Su, Shih-Hsun Chang
  • Publication number: 20240147685
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain (S/D) epitaxial feature disposed over a substrate, a second S/D epitaxial feature adjacent the first S/D epitaxial feature, and a hybrid fin disposed between the first and second S/D epitaxial features. The hybrid fin includes a first dielectric material, a second dielectric material disposed on the first dielectric material, a dielectric layer surrounding the first and second dielectric materials, and a high-k dielectric layer disposed in the first and second dielectric materials. The high-k dielectric layer has an upper surface located at a level between a level of an upper surface of the second dielectric material and a level of a lower surface of the second dielectric material.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 2, 2024
    Inventors: Wen-Li Chiu, Chun-Sheng Liang
  • Publication number: 20240113188
    Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a first gate line, a second gate line, and a first auxiliary gate portion. The semiconductor substrate comprises a semiconductor fin. The semiconductor fin extends substantially along a first direction. The first gate line and the second gate line extend substantially along a second direction different form the first direction from a top view. The first auxiliary gate portion connects the first gate line to the second gate line from the top view.
    Type: Application
    Filed: March 27, 2023
    Publication date: April 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Li CHIU, Yi-Juei LEE, Yu-Jie YE, Chi-Hsin CHANG, Chun-Jun LIN
  • Publication number: 20230411492
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a dummy gate stack over a substrate and forming a dielectric layer laterally surrounding the dummy gate stack. The method also includes introducing dopants into an upper portion of the dielectric layer and removing the dummy gate stack to form a trench surrounded by the dielectric layer. The method further includes forming a metal gate stack in the trench.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yi CHANG, Wen-Li CHIU, Hsin-Che CHIANG, Chun-Sheng LIANG
  • Patent number: 11101385
    Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap in such a way that the mask layer and the fin structure are separated by an air gap in the gap.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Li Chiu, Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 11049775
    Abstract: Provided is a semiconductor device including a first fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure over a first semiconductor fin and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer has a bar-shaped structure, the second layer has a U-shaped structure encapsulating sidewalls and a bottom surface of the first layer, and the first layer and the second layer include different materials. A method of manufacturing the semiconductor device is also provided.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ching Huang, Cheng-Chien Li, Wen-Li Chiu
  • Publication number: 20200091345
    Abstract: A method for forming a FinFET device structure is provided. The method for forming a FinFET device structure includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method for forming a FinFET device structure also includes forming a first spacer over a sidewall of the gate structure and forming a second spacer over the first spacer. The method for forming a FinFET device structure further includes etching the second spacer to form a gap and forming a mask layer over the gate structure and the first spacer after the gap is formed. In addition, the mask layer extends into the gap in such a way that the mask layer and the fin structure are separated by an air gap in the gap.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Inventors: Wen-Li CHIU, Hsin-Che CHIANG, Chun-Sheng LIANG, Kuo-Hua PAN
  • Publication number: 20200043809
    Abstract: Provided is a semiconductor device including a first fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure over a first semiconductor fin and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer has a bar-shaped structure, the second layer has a U-shaped structure encapsulating sidewalls and a bottom surface of the first layer, and the first layer and the second layer include different materials. A method of manufacturing the semiconductor device is also provided.
    Type: Application
    Filed: June 27, 2019
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Ching Huang, Cheng-Chien Li, Wen-Li Chiu
  • Patent number: 10529861
    Abstract: FinFET structures and methods of forming the same are disclosed. A device includes a semiconductor fin. A gate stack is on the semiconductor fin. The gate stack includes a gate dielectric on the semiconductor fin and a gate electrode on the gate dielectric. The gate electrode and the gate dielectric have top surfaces level with one another. A first inter-layer dielectric (ILD) is adjacent the gate stack over the semiconductor fin. The first ILD exerts a compressive strain on the gate stack.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Wei-Ting Chien, Chun-Feng Nieh, Wen-Li Chiu, Huicheng Chang, Chun-Sheng Liang
  • Patent number: 10128156
    Abstract: A FinFET device and a method for fabricating the same are provided. In the method for fabricating the FinFET device, at first, a semiconductor substrate having fin structures is provided. Then, a dielectric layer and a dummy gate structure are sequentially formed on the semiconductor substrate. The dummy gate structure includes two dummy gate stacks, a gate isolation structure formed between and adjoining the dummy gate stacks, and two spacers sandwiching the dummy gate stacks and the gate isolation structure. Then, the dummy gate stacks are removed to expose portions of the dielectric layer and to expose sidewalls of portions of the spacers. Thereafter, an oxidizing treatment is conducted on the exposed portions of the dielectric layer and the portions of the spacers to increase quality of the dielectric layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Che Chiang, Wen-Li Chiu, Chun-Sheng Liang, Jeng-Ya David Yeh
  • Publication number: 20180145177
    Abstract: FinFET structures and methods of forming the same are disclosed. A device includes a semiconductor fin. A gate stack is on the semiconductor fin. The gate stack includes a gate dielectric on the semiconductor fin and a gate electrode on the gate dielectric. The gate electrode and the gate dielectric have top surfaces level with one another. A first inter-layer dielectric (ILD) is adjacent the gate stack over the semiconductor fin. The first ILD exerts a compressive strain on the gate stack.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Yu-Chang Lin, Wei-Ting Chien, Chun-Feng Nieh, Wen-Li Chiu, Huicheng Chang, Chun-Sheng Liang