Patents by Inventor Wen-Liang Luo

Wen-Liang Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7781235
    Abstract: A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs) connected to the plurality of through-silicon vias, wherein the UBMs are on the first side of the stack structure. The method further includes attaching a handling wafer on the second side of the stack structure; performing a chip probing process; and removing the handling wafer from the stack structure.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: August 24, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Liang Luo, Yung-Liang Kuo, Hsu Ming Cheng
  • Patent number: 7598523
    Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: October 6, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Liang Luo, Yung-Liang Kuo, Hsu Ming Cheng
  • Publication number: 20080272372
    Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads.
    Type: Application
    Filed: March 19, 2007
    Publication date: November 6, 2008
    Inventors: Wen-Liang Luo, Yung-Liang Kuo, Hsu Ming Cheng
  • Publication number: 20080153187
    Abstract: A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs) connected to the plurality of through-silicon vias, wherein the UBMs are on the first side of the stack structure. The method further includes attaching a handling wafer on the second side of the stack structure; performing a chip probing process; and removing the handling wafer from the stack structure.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Inventors: Wen-Liang Luo, Yung-Liang Kuo, Hsu Ming Cheng