Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.

Abstract: A memory device is provided and includes a memory array. The memory array includes multiple strings, each of the strings including multiple memory cells and at least one compensation cell that are coupled in series to a corresponding one of multiple bit lines. In a read operation, the at least one compensation cell in each of the strings has a resistance responsive to at least one compensation voltage applied on the at least one compensation cell to adjust a read current in the corresponding bit line to a current value. The resistance is associated with a number of programmed cells in the memory cells coupled to the corresponding bit line.

Abstract: A memory device and a reading method thereof are provided. The memory device at least includes a first word line, a second word line and a third word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells connected to the first word line. A recognition procedure is executed in response to at least one memory cell has an error. A re-read procedure is executed on the memory cell. The recognition procedure includes: applying a pass voltage to the first word line; applying a recognition voltage to at least one of the second word line and the third word line. The re-read procedure including: applying a second read voltage to the first word line; and applying a second pass voltage to the second word line and a third pass voltage to the third word line.

Abstract: A memory device and a reading method thereof are provided. A second word line and a third word line are adjacent to a first word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells of the first word line. When a read error occurs, a re-read procedure is executed for some of the memory cells belonging to a state marginal group. The read procedure includes: applying a read voltage to the first word line; applying a first pass voltage to the second word line and the third word line. The re-read procedure includes: applying the read voltage to the first word line; applying a second pass voltage and a third pass voltage different from the first pass voltage to the second word line and the third word line respectively.

Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.

Abstract: A memory device and a method for operating selective erase scheme are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.

Abstract: Chiral liquid crystal compounds for use as dopants to be mixed with a liquid crystal host material, which may or may not be composed of chiral molecules, to form ferroelectric liquid crystal compositions. The chiral liquid crystal compounds are represented by the following formula: ##STR1## wherein: R.sub.1 is a C.sub.2 to C.sub.10 alkyl group, R.sub.2 is a C.sub.2 to C.sub.8 alkyl group;A is either ##STR2## m is an integer of 1 or 2; n is an integer of 1 or 2;p and q are integers of 0 or 1, provided that when p=0, q=0, and p=1, q=1; and* and ** indicate, independently of each other, S- or R-stereoisomeric structure.

Abstract: A liquid crystal composition containing an optically active or a ferroelectric liquid crystal compound represented by the following formula: ##STR1## wherein A can be either --CH.sub.2 -- or --CO--; R can be either an alkyl or alkoxyl group having 1 to 22 carbons: R' is an alkyl group having 2 to 8 carbons; x and y are integers of either 0 or 1, provided that when x=0, y.noteq.1; D can be a hydrogen or a halogen atom; and * represents a chiral center. The ferroelectric liquid crystals of the present invention exhibit optical and chemical stabilities, high-speed responsive, and high spontaneous polarization, and thus are excellent materials for use in making liquid crystal devices and liquid crystal light switching elements.

Abstract: Optically active compounds of general formulae ##STR1## wherein A is O or S, R.sub.1 is a hydrogen atom, an alkyl group having 1-22 carbon atoms, a hydroxy containing alkyl group, para-alkyl substituted phenyl, para-alkyl substituted biphenyl, hydroxyphenyl, hydroxybiphenyl or tosyl; R.sub.2 is an alkyl group having 2-8 carbon atoms; m is an integer of 0-5, n is 0 or 1, where when m=0, n is not 1; p is 0 or 1; q is 0 or 1; D and E are independently H or a halogen atom; R.sub.3 is a linear alkyl group having 1 to 22 carbon atoms; and * and ** are asymmetric centers.

Abstract: An optically active lactic acid derivative having the formula (1a): ##STR1## wherein A is O or S; B is --(CH.sub.2).sub.m -- or --(CH.sub.2).sub.n --O; R1 is an alkoxy group having 1-22 carbon atoms, a phenolate, a substituted phenolate, a hydroxy group, or a halogen atom; R2 is an alkyl group having 2-8 carbon atoms; m is 0, 1, 2, 3 or 4; n is 2, 3, 4 or 5; C* is an asymmetric carbon atom. Liquid crystal compositions and liquid crystal devices containing the above mentioned derivatives are also disclosed.

Abstract: A liquid crystal composition containing an optically active or a ferroelectric liquid crystal compound represented by the following formula: ##STR1## wherein: A is selected from the group consisting of oxygen and sulfur; B is selected from the group consisting of --(CH.sub.2).sub.m -- and --(CH.sub.2).sub.n --O--; R is an alkyl or alkoxyl group having 1 to 22 carbons; R' is an alkyl group having 2 to 8 carbons or an ether group having 2 to 8 carbons; m is an integer from 0 to 4; n is an integer from 2 to 5; k is an integer of 0 or 1; l is an integer of 0 or 1; C and D are selected form the group consisting of hydrogen atom and halogen atoms, and * represents a chiral center. The ferroelectric liquid crystals of the present invention exhibit optical and chemical stabilities, high-speed switching characteristic and high spontaneous polarization, and thus are excellent materials for use in liquid crystal devices and liquid crystal light switching elements.