Patents by Inventor Wen-Liang Yeh

Wen-Liang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367694
    Abstract: A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.
    Type: Application
    Filed: May 26, 2021
    Publication date: November 17, 2022
    Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Ruey-Chyr Lee
  • Patent number: 11502177
    Abstract: A high-electron mobility transistor includes a substrate, a GaN channel layer over the substrate, an AlGaN layer over the GaN channel layer, a gate recess in the AlGaN layer, a source region and a drain region on opposite sides of the gate recess, a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively, a p-GaN gate layer in and on the gate recess; and a re-grown AlGaN film on the AlGaN layer, on the GaN source layer and the GaN drain layer, and on interior surface of the gate recess.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 15, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11489048
    Abstract: A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Publication number: 20220344133
    Abstract: A method for forming a layer includes following operations. A workpiece is received in an apparatus for deposition. The apparatus for deposition includes a chamber, a pedestal disposed in the chamber to accommodate the workpiece, and a ring disposed on the pedestal. The ring includes a ring body having a first top surface and a second top surface and a barrier structure disposed between the first top surface and the second top surface. A vertical distance is defined by a top surface of the barrier structure and a top surface of the workpiece. The vertical distance is between approximately 0 mm and approximately 50 mm. A target disposed in the apparatus for deposition is sputtered. A sputtered material is deposited onto a top surface of the workpiece to form a layer. The barrier structure alters an electrical density distribution during the depositing the sputter material.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: HSIN-LIANG CHEN, WEN-CHIH WANG, CHIA-HUNG LIAO, CHENG-CHIEH CHEN, YI-MING YEH, HUNG-TING LIN, YUNG-YAO LEE
  • Publication number: 20220287182
    Abstract: An embedded component structure includes a board, an electronic component, and a dielectric material layer. The board has a through cavity. The board includes an insulating core layer and a conductive member. The insulating core layer has a first surface and a second surface opposite thereto. The through cavity penetrates the insulating core layer. The conductive member extends from a portion of the first surface along a portion of the side wall of the through cavity to a portion of the second surface. The electronic component includes an electrode. The electronic component is disposed in the through cavity. The dielectric material layer is at least filled in the through cavity. The connection circuit layer covers and contacts the conductive member and the electrode. A manufacturing method of an embedded component structure is also provided.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Yu-Hua Chen, Chun-Hsien Chien, Wen-Liang Yeh, Ra-Min Tain
  • Patent number: 11348869
    Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: May 31, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Chien-Chou Chen, Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Patent number: 11201123
    Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 ?m to 10 ?m.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 14, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Po-Chen Lin, Wen-Liang Yeh, Chien-Chou Chen
  • Publication number: 20210219435
    Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.
    Type: Application
    Filed: April 1, 2021
    Publication date: July 15, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Patent number: 10999939
    Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Publication number: 20210074633
    Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
    Type: Application
    Filed: November 22, 2020
    Publication date: March 11, 2021
    Inventors: Chien-Chou CHEN, Chun-Hsien CHIEN, Wen-Liang YEH, Wei-Ti LIN
  • Patent number: 10879167
    Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 29, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Chien-Chou Chen, Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Publication number: 20200194384
    Abstract: A substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The conductive region includes a plurality of conductive micro vias. The conductive micro vias penetrate through the glass substrate. The conductive micro vias are electrically connected to the first circuit layer and the second circuit layer, and the conductive micro vias have a via size of 2 ?m to 10 ?m.
    Type: Application
    Filed: November 5, 2019
    Publication date: June 18, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Po-Chen Lin, Wen-Liang Yeh, Chien-Chou Chen
  • Publication number: 20200163215
    Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 21, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Wen-Liang Yeh, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Patent number: 10660202
    Abstract: A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Wen-Liang Yeh, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Publication number: 20200144179
    Abstract: A chip packaging structure includes a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure includes a first and a second circuit layer, and a conductive pad. The second circuit layer is disposed on and electrically connected to the first circuit layer. The conductive pad is electrically connected to the second circuit layer. The chip is disposed on the circuit redistribution structure and electrically connected to the second circuit layer. The sealing layer having an opening and a groove covers the chip and the circuit redistribution structure. The opening exposes the conductive pad. A portion of the groove communicates with the opening. The antenna pattern includes a first and a second portion. The first portion covers sidewalls of the opening and is electrically connected to the conductive pad. The second portion is filled in the groove and electrically connected to the first portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 7, 2020
    Inventors: Chien-Chou CHEN, Chun-Hsien CHIEN, Wen-Liang YEH, Wei-Ti LIN
  • Publication number: 20190380212
    Abstract: A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.
    Type: Application
    Filed: August 8, 2019
    Publication date: December 12, 2019
    Applicant: Unimicron Technology Corp.
    Inventors: Chun-Hsien Chien, Wen-Liang Yeh, Wei-Ti Lin
  • Publication number: 20190380200
    Abstract: An embedded component structure including a circuit board, an electronic component, a dielectric layer and a connection circuit layer and a manufacturing method thereof is provided. The circuit board has a through hole and includes a core layer, a first circuit layer, and a second circuit layer. The first circuit layer and the second circuit layer are disposed on the core layer. The through hole penetrates the first circuit layer and the core layer. The electronic component including a plurality of connection pads is disposed within the through hole where the dielectric layer is filled in. The Young's modulus of the core layer is greater than the Young's modulus of the dielectric layer. The connection circuit layer covers and contacts a first electrical connection surface of the first circuit layer and at least one of a second electrical connection surface of each of the connection pads. A manufacturing method of an embedded component structure is also provided.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 12, 2019
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Yu-Hua Chen, Chun-Hsien Chien, Wen-Liang Yeh, Ra-Min Tain
  • Patent number: 10461146
    Abstract: A package structure includes a substrate, a metal-insulator-metal capacitor, a circuit redistribution structure, and a chip. The metal-insulator-metal capacitor is disposed over the substrate and includes a first electrode, a second electrode, and an insulating layer. The circuit redistribution structure is disposed over the metal-insulator-metal capacitor and includes a first circuit redistribution layer and a second circuit redistribution layer. The first circuit redistribution layer includes a first wire electrically connected to the first electrode and a second wire electrically connected to the second electrode. The second circuit redistribution layer is disposed on the first circuit redistribution layer and includes a third wire electrically connected to the first wire and a fourth wire electrically connected to the second wire. The chip is disposed over the circuit redistribution structure and electrically connected to the third wire and the fourth wire.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 29, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Wen-Liang Yeh, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Publication number: 20030205624
    Abstract: A card fabrication method of the invention uses ABS plastics to form a card body of the card. The fabrication method of the invention is used to manufacture various types of cards such as bankcards. The ABS material is injection molded to form the card body. While injection molding the card body, different additives and colorant agents are incorporated to the ABS to obtain a card body that is easily differentiated via a specific color aspect. The specific color aspect is in accordance with a specific card emitter. Printing is simultaneously performed on two faces of the card body to achieve the differentiable card. By attributing specific color aspects to specific card emitters and, counterfeit cards is therefore easily differentiated from authentic cards by the color aspect of the card body.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Inventors: Chih-Yang Huang, Tsung-Chao Li, Wen-Liang Yeh
  • Publication number: 20030205623
    Abstract: The invention provides a method of manufacturing a card such as bankcards provided with an anti-counterfeit differentiable mark. A stamper is fabricated by engraving and plate-making methods, the stamper being engraved with a feature pattern provided by a client, such as bank logo and trademarks. The feature pattern of the stamper is transferred onto a surface of a card by injection molding. A metallic layer is formed on the card by plating. A printing layer is finally formed on the card by printing. Hence fabricated, the card is provided with a text and/or graphics pattern similar to the effects of a hologram pattern.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Inventors: Chih-Yang Huang, Tsung-Chao Li, Wen-Liang Yeh