Patents by Inventor Wen-Lin Chen
Wen-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250101171Abstract: A modified polyethylene terephthalate copolyester, including three fragments shown as [Fragment 1], [Fragment 2], and [Fragment 3] in the specification, is provided.Type: ApplicationFiled: October 26, 2023Publication date: March 27, 2025Applicant: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Chi-Lin Chen, Wen-Hua Lu
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Publication number: 20250092200Abstract: A preparation method of a modified bismaleimide resin includes the following steps. Maleic anhydride is mixed with a bisamine compound to obtain a corresponding mixture. The mixture is heated. The bisamine compound has a main chain structure or fragment represented by Formula A, Formula B, or Formula C as described in the description.Type: ApplicationFiled: November 7, 2023Publication date: March 20, 2025Applicant: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Chi-Lin Chen, Wen-Hua Lu
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Publication number: 20250077289Abstract: The present invention provides a method for optimizing graphics-processing unit (GPU) utilization and a system thereof. The method includes the following steps: receiving an application workload which is to be executed on the GPU; predicting GPU resource requirements for the application workload; scheduling the application workload according to the prediction of the GPU resource requirements; dynamically allocating and deallocating GPU resources based on the prediction of the GPU resource requirements for the application workload; and executing the application workload on the GPU.Type: ApplicationFiled: August 28, 2023Publication date: March 6, 2025Inventors: Wen-Shyen Chen, Ming-Jye Sheu, Henry Hong-Yi Tzeng, Sheng-Lin Wu
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Publication number: 20250081730Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.Type: ApplicationFiled: June 26, 2024Publication date: March 6, 2025Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
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Publication number: 20250062184Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: November 4, 2024Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 12165946Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: GrantFiled: July 26, 2023Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Publication number: 20230378021Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: July 26, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 11784106Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: GrantFiled: July 29, 2022Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 11508640Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: GrantFiled: May 14, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Publication number: 20220367315Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Publication number: 20220050347Abstract: A method for fast and convenient manufacture of liquid crystal display panels of different sizes without retooling provides an array substrate having a first display area of a first size. A closed-shaped sealant is coated onto the array substrate, the sealant defining a second display area of a second size, the second display area including an actual display area and an undesired display area adjacent to the actual display area and the sealant. Liquid crystals are applied in the second display area and sealing and coupling are carried out to obtain a liquid crystal cell, the liquid crystal cell being cut along an outer periphery of the sealant to obtain a working liquid crystal display panel of the desired size.Type: ApplicationFiled: July 8, 2021Publication date: February 17, 2022Inventors: ZHENG-XIA HE, NING FANG, YUAN XIONG, HUI WANG, WEN-LIN CHEN, CHIH-CHUNG LIU
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Publication number: 20220036780Abstract: An electrical conductivity test structure for testing an electrical conductivity of target traces in a display panel includes a controller, a first conductive layer, and a second conductive layer. The first conductive layer includes first and second traces. The at least one first trace and the at least one second trace are connected in parallel. Each first trace connects with the target trace and with the controller and each second trace connects with the target trace and with the controller. The second conductive layer connects with the first trace but is electrically insulated from the second trace. The second conductive layer transmits test signals to the first trace to test electrical conductivity between the controller and the target trace.Type: ApplicationFiled: March 19, 2021Publication date: February 3, 2022Inventors: QI XU, RUI LI, YUAN XIONG, HUI WANG, WEN-LIN CHEN, CHIH-CHUNG LIU
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Patent number: 11017738Abstract: A gate driving circuit which allows narrower framing of a display screen includes cascade-connected gate driving modules. Each gate driving module is electrically coupled to first and second scan lines and outputs scanning signals to the first and the second scan lines in a time-division manner in response to first and second clock signals. Each gate driving module includes an input transistor, and first and second output transistors. The input transistor receives a trigger signal for activating the gate driving module. The input transistor controls the first output transistor to output first scanning signal to first scan line in response to the first clock signal and controls the second output transistor to output second scanning signal to the second scan line in response to the second clock signal.Type: GrantFiled: November 27, 2018Date of Patent: May 25, 2021Assignee: Century Technology (Shenzhen) Corporation LimitedInventors: Qi Xu, Ming-Tsung Wang, Wen-Lin Chen, Jing Zhu
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Publication number: 20200279790Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: May 14, 2020Publication date: September 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 10658263Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: GrantFiled: May 31, 2018Date of Patent: May 19, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Publication number: 20200013362Abstract: A gate driving circuit which allows narrower framing of a display screen includes cascade-connected gate driving modules. Each gate driving module is electrically coupled to first and second scan lines and outputs scanning signals to the first and the second scan lines in a time-division manner in response to first and second clock signals. Each gate driving module includes an input transistor, and first and second output transistors. The input transistor receives a trigger signal for activating the gate driving module. The input transistor controls the first output transistor to output first scanning signal to first scan line in response to the first clock signal and controls the second output transistor to output second scanning signal to the second scan line in response to the second clock signal.Type: ApplicationFiled: November 27, 2018Publication date: January 9, 2020Inventors: QI XU, MING-TSUNG WANG, WEN-LIN CHEN, JING ZHU
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Publication number: 20190371699Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
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Patent number: 8779892Abstract: A wireless illumination controller with the function to set the lowest driving power includes a microprocessor, a driver, an illumination control switch, and a wireless receiving module. The microprocessor is built in with an adjustable lowest power and connected with the driver, the illumination control switch, the wireless receiving module and a power processing module. The illumination control switch is used to set the lowest power of the microprocessor. After the wireless receiving module receives a wireless illumination adjustment command, the power of the driving signal output from the driver is controlled to be not lower than the lowest power. Therefore, when a user adjusts the illumination, the driving power is never lower than the lowest driving power of the corresponding light bulb, thereby avoiding flickering.Type: GrantFiled: December 29, 2011Date of Patent: July 15, 2014Assignee: Arc Technology Co., Ltd.Inventor: Wen-Lin Chen
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Publication number: 20140003019Abstract: A remotely controllable outlet assembly has a case, an outlet panel and a power remote control device. The outlet panel is mounted on the case. The power remote control device has a remote controller and a main control apparatus. The main control apparatus is mounted in the case and is electrically connected to a neutral wire, a live wire and an outlet of the outlet panel. The main control apparatus electrically connects or disconnects the neutral wire and the live wire to or from the outlet according to an operation command emitted from the remote controller. Therefore, the outlet is remotely controllable. The main control apparatus is embedded in the wall, so that the outlet assembly does not spoil the interior decoration of the house.Type: ApplicationFiled: September 11, 2012Publication date: January 2, 2014Inventors: Wen-Lin CHEN, Chi-Kan LIN, Chung-Chi CHIANG
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Publication number: 20130119885Abstract: A wireless illumination controller with the function to set the lowest driving power includes a microprocessor, a driver, an illumination control switch, and a wireless receiving module. The microprocessor is built in with an adjustable lowest power and connected with the driver, the illumination control switch, the wireless receiving module and a power processing module. The illumination control switch is used to set the lowest power of the microprocessor. After the wireless receiving module receives a wireless illumination adjustment command, the power of the driving signal output from the driver is controlled to be not lower than the lowest power. Therefore, when a user adjusts the illumination, the driving power is never lower than the lowest driving power of the corresponding light bulb, thereby avoiding flickering.Type: ApplicationFiled: December 29, 2011Publication date: May 16, 2013Inventor: Wen-Lin CHEN