Patents by Inventor Wen Ling Huang

Wen Ling Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190279933
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
  • Patent number: 10380962
    Abstract: A driving circuit applied to a LCD apparatus includes N driver chips, a signal source, a WOA wire, a COF wire. Each driver chip is COF-packaged and correspondingly coupled to L output channels. N and L are positive integers and N?2. The signal source is coupled to L output channels of the first driver chip. One terminal of WOA wire is coupled to L output channels of the second driver chip. One terminal of the COF wire is coupled between the signal source and a first output channel of the first driver chip and another terminal of the COF wire is coupled to another terminal of WOA wire. The resistance of COF wire is far smaller than a first internal resistance between the first output channel and L-th output channel of first driver chip and the resistance of WOA wire is substantially equal to first internal resistance.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 13, 2019
    Assignee: Raydium Semiconductor Corporation
    Inventors: E-Ling Huang, Chih Chuan Huang, Wen-Tsung Lin
  • Publication number: 20190229123
    Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Tsun-Kai TSAO, Hung-Ling SHIH, Po-Wei LIU, Shun-Shing YANG, Wen-Tuo HUANG, Yong-Shiuan TSAIR, S.K. YANG
  • Patent number: 10332477
    Abstract: A display device includes a display array and a driving circuit. The display array includes at least one scan line. The driving circuit drives the display array and includes a timing controller and a gate driver. The timing controller controls a refresh rate of the display array at a first frequency or a second frequency, where the first frequency is higher substantially than the second frequency. The gate driver switches between supplying an enable voltage signal and a disable voltage signal to the scan line. Under the first or frequency, a corresponding first or second voltage difference exists between the enable voltage signal and the disable voltage signal. The first voltage difference is substantially greater than the second voltage difference, and the enable voltage signal has a same enable period.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 25, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yueh-Hung Chung, Ya-Ling Hsu, Han-Ming Chen, Chen-Hsien Liao, Gang-Yi Lin, Wen-Chen Lo, Ming-Chang Shih, Hsueh-Ying Huang
  • Publication number: 20190172753
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a first gate structure and a second gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; forming a hard mask on the first metal gate and the second metal gate; removing part of the hard mask, the second metal gate, and part of the fin-shaped structure to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.
    Type: Application
    Filed: January 2, 2018
    Publication date: June 6, 2019
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10312146
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 4, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 10304772
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 28, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
  • Publication number: 20190157281
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.
    Type: Application
    Filed: November 29, 2018
    Publication date: May 23, 2019
    Inventors: ShihKuang YANG, Yong-Shiuan TSAIR, Po-Wei LIU, Hung-Ling SHIH, Yu-Ling HSU, Chieh-Fei CHIU, Wen-Tuo HUANG
  • Patent number: 9627765
    Abstract: Embodiments of an optically transparent antenna are generally described herein. In some embodiments, the optically transparent antenna may comprise a plurality of electrically-isolated conductive patches arranged on a non-conductive surface. A combination of a size of the conductive patches and a spacing between the conductive patches is less than a human visual acuity for a predetermined viewing distance so that the patches are not be visible or perceptible to a human. In some embodiments, optically transparent antenna may serve as one or more antennas on a mobile platform.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Helen Kankan Pan, Wen-Ling Huang, Harry G. Skinner
  • Publication number: 20150087323
    Abstract: Certain embodiments herein are directed to managing wireless spectrum, which may include recommending or transmitting spectrum usage changes to one or more wireless devices. A spectrum management system comprising one or more computers may receive spectrum usage information associated with one or more wireless devices. The spectrum management system may generate a spectrum usage map based on the received information. Based on the spectrum usage map, a spectrum usage change is determined and transmitted to one or more wireless devices. The wireless devices may change their operation in accordance with the spectrum usage change.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Inventors: Srikathyayani Srikanteswara, Carlos Cordeiro, Kerstin Johnsson, Anthony Lamarca, Jaideep Moses, Wen-Ling Huang, Christian Maciocco, Shilpa Talwar, Meiyuan Zhao, Jeffrey Foerster, Xue Yang
  • Publication number: 20150029064
    Abstract: Embodiments of an optically transparent antenna are generally described herein. In some embodiments, the optically transparent antenna may comprise a plurality of electrically-isolated conductive patches arranged on a non-conductive surface. A combination of a size of the conductive patches and a spacing between the conductive patches is less than a human visual acuity for a predetermined viewing distance so that the patches are not be visible or perceptible to a human. In some embodiments, optically transparent antenna may serve as one or more antennas on a mobile platform.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Inventors: Helen Kankan Pan, Wen-Ling Huang, Harry G. Skinner
  • Publication number: 20110031588
    Abstract: An improved varactor diode (20, 50) having first (45) and second (44) terminals is obtained by providing a substrate (22, 52) having a first surface (21, 51) in which are formed isolation regions (28, 58) separating first (23, 53) and second (25, 55) parts of the diode (20, 50). A varactor junction (40, 70) is formed in the first part (23, 53) and having a first side (35, 66) coupled to the first terminal (45) and a second side (34, 54) coupled to the second terminal (44) via a sub-isolation buried layer (SIBL) region (26, 56) extending under the bottom (886) and partly up the sides (885) of the isolation regions (28, 58) to a further doped region (30, 32; 60, 62) ohmically connected to the second terminal (44). The first part (36, 66) does not extend to the SIBL region (26, 56). The varactor junction (40, 70) desirably comprises a hyper-abrupt doped region (34, 54).
    Type: Application
    Filed: August 6, 2009
    Publication date: February 10, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Pamela J. Welch, Wen Ling Huang, David G. Morgan, Hernan A. Rueda, Vishal P. Trivedi