Abstract: A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).

Abstract: A two stage threshold adjust implantation process is performed after field oxidation to avoid the effects of dopant redistribution and segregation. At any of several steps in a manufacturing process, only routine implant energy and dose adjustments are required to create a first and a second dopant profile (110, 120) that result in the reduction of edge leakage and threshold voltage sensitivity to device layer thickness of a semiconductor device on a semiconductor on insulator substrate.

Abstract: A semiconductor-on-insulator transistor (10) has a channel region (30) in a semiconductor film (16) under a gate insulating layer (26). The channel region has a top dopant concentration N.sub.T at a top surface (32) of the film that is significantly greater than a bottom dopant concentration N.sub.B at a bottom surface (34) of the film. This non-uniform doping profile provides an SOI device that operates in a fully-depleted mode, yet permits thicker films without a significant degradation of sub-threshold slope.

Abstract: A method of adjusting a threshold voltage for a semiconductor device on a semiconductor on insulator substrate includes performing a threshold voltage adjustment implant (25) after formation of a gate structure (16) to reduce the diffusion of implanted dopant (26). Reducing dopant diffusion eliminates the narrow channel effect which degrades device performance. Implanting the dopant (26) after formation of the gate structure (16) simplifies processing of semiconductor device (28) by eliminating a photolithography step which is accomplished by utilizing photoresist (21) used for a source and drain implant (22).

Abstract: A method for forming an improved base link for a bipolar transistor is provided. The wall where the base link (44) is formed is substantially vertical (32,34). An oxide mask (24) is use during etching of the polysilicon layer (18) that provides the wall, instead of a conventional photoresist mask. The preferred method is compatible with manufacturing BiCMOS devices.

Abstract: This invention pertains to a self-aligned, trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects.

Abstract: In a process for fabricating a bipolar transistor with a single polysilicon layer, a silicon nitride layer 22 and a phospho-silicate glass layer 24 are formed on top of the polysilicon layer and the link oxide layers. The glass layer 24 has a high etch selectivity compared to the nitride layer 22 so that the glass layer may be overetched above the emitter polysilicon region without overetching the link oxide. The nitride layer is then removed by etching without significantly affecting the link oxide layer. Thus the emitter metal contact may be self-aligned on top of the emitter polysilicon region 14, 114.

Abstract: This invention pertains to a self-aligned trench-isolated emitter structure and the method for forming same. The emitter structure comprises a portion of a bipolar transistor which exhibits improved function due to the emitter structure. A single layer of conductive material forms both the emitter and base contacts in the transistor structure, which structure has particularly shallow emitter and base junctions (about 0.15 micrometer or less). The self-aligned emitter contact, isolated from the base contact by a dielectric filled trench, permits overall size reduction of the device, whereby junction area and accompanying leakage across junctions is reduced. In addition, when the structure of the bipolar transistor is such that the trench isolates the emitter area from both the base contact and the extrinsic base, it is possible to provide improved base conductivity without generating peripheral transistor effects.