Patents by Inventor Wen-Ling Margaret Huang

Wen-Ling Margaret Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12263599
    Abstract: Various aspects of methods, systems, and use cases include techniques for training or using a model to control a robot. A method may include identifying a set of action primitives applicable to a set of robots, receiving information corresponding to a task (e.g., a collaborative task), and determining at least one action primitive based on the received information. The method may include training a model to control operations of at least one robot of the set of robots using the received information and the at least one action primitive.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Venkat Natarajan, Arjun Kg, Gagan Acharya, Amit Sudhir Baxi, Rita H. Wouhaybi, Wen-Ling Margaret Huang
  • Publication number: 20210229281
    Abstract: Various aspects of methods, systems, and use cases include techniques for training or using a model to control a robot. A method may include identifying a set of action primitives applicable to a set of robots, receiving information corresponding to a task (e.g., a collaborative task), and determining at least one action primitive based on the received information. The method may include training a model to control operations of at least one robot of the set of robots using the received information and the at least one action primitive.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 29, 2021
    Inventors: Venkat Natarajan, Arjun Kg, Gagan Acharya, Amit Sudhir Baxi, Rita H. Wouhaybi, Wen-Ling Margaret Huang
  • Patent number: 5920093
    Abstract: A semiconductor device (120) is formed in a silicon-on-insulator (SOI) substrate (135). The semiconductor device (120) has a channel region (126) that is controlled by a gate structure (129). The channel region (126) has a doping profile that is essentially uniform where the channel region (126) is under the gate structure (129). This eliminates the parasitic channel region that is common with conventional field effect transistors (FETs) that are formed in SOI substrates. Consequently, the semiconductor device (120) of the present invention does not suffer from the "kink" problem that is common to conventional FET devices.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: July 6, 1999
    Assignee: Motorola, Inc.
    Inventors: Wen Ling Margaret Huang, Ying-Che Tseng
  • Patent number: 5780352
    Abstract: A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: July 14, 1998
    Assignee: Motorola, Inc.
    Inventors: Heemyong Park, Wen-Ling Margaret Huang, Juergen Foerstner, Marco Racanelli
  • Patent number: 5670389
    Abstract: A silicon-on-insulator semiconductor device (40) having laterally-graded channel regions (23A, 24A) and a method of making the silicon-on-insulator semiconductor device (40). The silicon-on-insulator semiconductor device (40) has a gate structure (16) having sidewalls (19, 21) on a semiconductor layer (12). Lightly doped regions (26A, 27A) extend through an entire thickness of a portion of the semiconductor layer (12) under the sidewalls (19, 21). A laterally-graded channel region (23A) is formed below the gate structure (16) and abutting one (26A) of the lightly doped regions. A source (33) is formed in a first (26A) of the lightly doped regions and a drain region (34) is formed in a second (27A) of the lightly doped regions.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: September 23, 1997
    Assignee: Motorola, Inc.
    Inventors: Wen-Ling Margaret Huang, Hyungcheol Shin, Marco Racanelli