Abstract: A single round advanced encryption standard circuit module includes a substitution byte/inverse substitution byte unit, configured to substitute elements of an input state array to generate an output state array and to respectively generate a first state array, a plurality of second state arrays, a third state array, a plurality of fourth state arrays and the output state array according to a first tier circuit unit, a second tier circuit unit, a third tier circuit unit, a fourth tier circuit unit and a fifth tier circuit unit; wherein the first state array, the plurality of second state arrays, the third state array and the plurality of fourth state arrays are represented by register-transfer level codes; wherein the substitution byte/inverse substitution byte unit is implemented by composite field arithmetic of sharing operators and operands.

Abstract: A single round advanced encryption standard circuit module includes a substitution byte/inverse substitution byte unit, configured to substitute elements of an input state array to generate an output state array and to respectively generate a first state array, a plurality of second state arrays, a third state array, a plurality of fourth state arrays and the output state array according to a first tier circuit unit, a second tier circuit unit, a third tier circuit unit, a fourth tier circuit unit and a fifth tier circuit unit; wherein the first state array, the plurality of second state arrays, the third state array and the plurality of fourth state arrays are represented by register-transfer level codes; wherein the substitution byte/inverse substitution byte unit is implemented by composite field arithmetic of sharing operators and operands.

Abstract: A system and a method for reducing computational complexity of neural networks are revealed. The method includes the steps of inputting weight values, input values and an enable signal into a first accumulator for starting inner product computation of the weight values and the input values by the enable signal and then performing a shift of the weight values and the input values; shifting a deviation value and performing an add operation of the shifted deviation value and both the weight values and the input values already being processed to get a first output value; and checking if the first output value is less than a threshold value and outputting a result value of zero (0) if the first output value is less than the threshold value. Thereby computational power of the neural network is decreased owing to omission of a part of computational process.

Abstract: A symbol time synchronization method for OFDM systems is disclosed. The invention presents a joint maximum-likelihood (ML) synchronization method for symbol time offset (STO) in OFDM systems. The method is developed in frequency domain under time-variant multipath channels. By analyzing the received frequency-domain data, a mathematical model for the joint effects of symbol time offset (STO), carrier frequency offset (CFO) and sampling clock frequency offset (SCFO) is derived. The results are used to formulate a log-likelihood function of two consecutive symbols. The joint estimation's method is robust, because it exhibits high performances in high mobility and time-variant multipath fading channels.

Abstract: A symbol time synchronization method for OFDM systems is disclosed. The invention presents a joint maximum-likelihood (ML) synchronization method for symbol time offset (STO) for OFDM systems. The method is developed in frequency-domain under time-variant multipath channels. By analyzing the received frequency-domain data, a mathematical model for the joint effects of symbol time offset (STO), carrier frequency offset (CFO) and sampling clock frequency offset (SCFO) is derived. The results are used to formulate a log-likelihood function of two consecutive symbols. The joint estimation's method is robust, because it exhibits high performances in high mobility and time-variant multipath fading channels.

Abstract: A method for implementing Advanced Encryption Standards (AES) by a very long instruction word (VLIW) architecture processor. The method includes inputting the instructions for AES into the processor, decoding and scheduling the input instructions, controlling at least one of a plurality of multiplexers to output data from a first register of the processor and/or an arithmetic logic unit to the first register and/or the arithmetic logic unit according to the decoded and scheduled instructions, controlling the arithmetic logic unit to perform operations, and outputting results of the operations to the plurality of the multiplexers.

Abstract: A method for controlling an instruction memory (IM) of an embedded system. The embedded system is electrically connected to a memory device used for storing a plurality of program code segments. The embedded system includes the IM and an execution unit. The steps of the method are setting up a look-up table for recording the operation status of the IM, and determining if a specific program code segment of the program code segments has been stored in the IM or not according to the look-up table when the execution unit selects the specific program code segment to execute. If the specific program code segment has been stored in the IM, the execution unit reads the specific program code segment from the IM. If not, the execution unit loads the specific program code segment from the memory device and executes it.

Abstract: A method for managing a buffer memory in a crypto engine includes defining an IO writing address, a program reading address, a program writing address, and an IO reading address in the buffer memory. Input data is written into the IO writing address, and then the crypto engine reads the input data beginning at the program reading address to perform encryption or decryption processes. After the encryption or decryption processes, result of the processes is written into the program writing address, and then the result is read beginning at the IO reading address. When the IO writing address is different from the program reading address, the crypto engine is controlled to read the input data. When the program writing address is different from the IO reading address, the buffer memory is controlled to output the result.

Abstract: A very long instruction word (VLIW) architecture has a VLIW input port for sequentially inputting a plurality of VLIWs, a decoder for decoding a plurality of instructions of the VLIWs, at least a register, a plurality of data buses, a plurality of arithmetic logic units (ALUs) for executing the instructions, and a plurality of multiplexers. Each output port of the multiplexers is connected to one of the ALUs, and each input port of the multiplexers is connected to the register and output ports of the ALUs via the data buses. Each of the multiplexers selects two outputs from the outputs of the register and the ALUs so that the connected ALU executes one of the instructions to operate the two selected outputs.

Abstract: The present invention relates to a dynamic built-in self-skip method used for shared memory fault recovery. The method employs the mapping relationship between the packet buffer and free link table under the shared memory structure. First, we record the blocks in the free link table corresponding to the defective rows in the packet buffer without carrying out initialization to the blocks recorded as fail, so that they do not enter the package switching activity. Therefore the defective rows of the memory mapping to fail blocks do not proceed with the read/write process, in other words, accomplishing the object of fault recovery. The recovery method is not dependent on the memory architecture and complex algorithms, and thus it may be easily associated with designs of various systems and increases chip yield.