Abstract: A method of making a semiconductor device includes comparing a thickness profile of a surface of a wafer with a reference value using a control unit. The method further includes transmitting a control signal to an adjustable nozzle based on the comparison of the thickness profile and the reference value. The method further includes rotating the adjustable nozzle about a longitudinal axis of the adjustable nozzle in response to the control signal.

Abstract: A method of making a semiconductor device includes comparing a thickness profile of a surface of a wafer with a reference value using a control unit. The method further includes transmitting a control signal to an adjustable nozzle based on the comparison of the thickness profile and the reference value. The method further includes rotating the adjustable nozzle about a longitudinal axis of the adjustable nozzle in response to the control signal.

Abstract: A high density plasma chemical vapor deposition (HDP CVD) chamber includes a nozzle including a base having a hollow center portion for conducting gas; a tip coupled to the base and having an opening formed therein for conducting gas from the base to the exterior of the nozzle. The HDP CVD chamber further includes a baffle positioned in a top portion of the HDP CVD chamber, wherein the baffle is equipped with an adjustable baffle nozzle.

Abstract: A high density plasma chemical vapor deposition (HDP CVD) chamber includes a nozzle including a base having a hollow center portion for conducting gas; a tip coupled to the base and having an opening formed therein for conducting gas from the base to the exterior of the nozzle. The HDP CVD chamber further includes a baffle positioned in a top portion of the HDP CVD chamber, wherein the baffle is equipped with an adjustable baffle nozzle.

Abstract: A method of controlling a position of an adjustable nozzle includes depositing a film on a surface of a wafer. The method includes measuring a thickness profile of the surface of the wafer. The method includes comparing the measurement of the thickness profile with a reference value using a control unit. The method includes transmitting a control signal to the adjustable nozzle to alter the position of the adjustable nozzle based on the result of the comparison. The adjustable nozzle includes a base having a hollow center portion for conducting gas, the base configured for connection to a gas source. The adjust nozzle includes a tip coupled to the base and having an opening for conducting gas from the base to the exterior of the nozzle, wherein the base is configured for pivoting about a longitudinal axis of the base in response to the control signal.

Abstract: A method of controlling a position of an adjustable nozzle includes depositing a film on a surface of a wafer. The method includes measuring a thickness profile of the surface of the wafer. The method includes comparing the measurement of the thickness profile with a reference value using a control unit. The method includes transmitting a control signal to the adjustable nozzle to alter the position of the adjustable nozzle based on the result of the comparison. The adjustable nozzle includes a base having a hollow center portion for conducting gas, the base configured for connection to a gas source. The adjust nozzle includes a tip coupled to the base and having an opening for conducting gas from the base to the exterior of the nozzle, wherein the base is configured for pivoting about a longitudinal axis of the base in response to the control signal.

Abstract: The description relates to an adjustable nozzle capable of pivoting about an axis of the nozzle and translating along the axis of the nozzle. A high density plasma chemical vapor deposition (HDP CVD) chamber houses a plurality of adjustable nozzles. A feedback control system includes a control unit coupled to the adjustable nozzle and the HDP CVD chamber to form a more uniform thickness profile of films deposited on a wafer in the HDP CVD chamber.

Abstract: A method for forming a semiconductor device structure and an apparatus for heating a semiconductor substrate are provided. The method includes spin coating a material layer over a semiconductor substrate. The method also includes heating the material layer by using a first heater above the semiconductor substrate and a second heater below the semiconductor substrate.

Abstract: The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first gate structure formed over a substrate. The semiconductor structure includes a first spacer formed on a sidewall of the first gate structure. In addition, a top surface of the first spacer is parallel to a top surface of the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first gate structure formed over a substrate. The semiconductor structure includes a first spacer formed on a sidewall of the first gate structure. In addition, a top surface of the first spacer is parallel to a top surface of the substrate.

Abstract: A method for forming a semiconductor device structure and an apparatus for heating a semiconductor substrate are provided. The method includes spin coating a material layer over a semiconductor substrate. The method also includes heating the material layer by using a first heater above the semiconductor substrate and a second heater below the semiconductor substrate.

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.

Abstract: Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed.

Abstract: The description relates to an adjustable nozzle capable of pivoting about an axis of the nozzle and translating along the axis of the nozzle. A high density plasma chemical vapor deposition (HDP CVD) chamber houses a plurality of adjustable nozzles. A feedback control system includes a control unit coupled to the adjustable nozzle and the HDP CVD chamber to form a more uniform thickness profile of films deposited on a wafer in the HDP CVD chamber.

Abstract: The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

Abstract: A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

Abstract: A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.