Patents by Inventor Wen-Lung Shieh

Wen-Lung Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8803595
    Abstract: This invention provides a common mode noise cancellation circuit for the unbalanced signals. The unbalanced signals come from a signal source with a first signal terminal and a second signal terminal having a first grounding potential. The common mode noise cancellation circuit comprises a grounding terminal and a subtractor. The grounding terminal with a second grounding potential is electrically coupled to the second signal terminal of the signal source through an impedance unit. The subtractor comprises a first receiving terminal, a second receiving terminal and a signal output terminal. The first receiving terminal and the second receiving terminal are electrically coupled to the first signal terminal and the second signal terminal respectively for receiving the unbalanced signals. The subtractor subtracts the noise coming from the first receiving terminal and the noise coming from the second receiving terminal to reduce the output noise of the signal output terminal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 12, 2014
    Assignee: C-Media Electronics, Inc.
    Inventors: Wen-Lung Shieh, Chih-Ying Huang
  • Publication number: 20140139284
    Abstract: This invention provides a common mode noise cancellation circuit for the unbalanced signals. The unbalanced signals come from a signal source with a first signal terminal and a second signal terminal having a first grounding potential. The common mode noise cancellation circuit comprises a grounding terminal and a subtractor. The grounding terminal with a second grounding potential is electrically coupled to the second signal terminal of the signal source through an impedance unit. The subtractor comprises a first receiving terminal, a second receiving terminal and a signal output terminal. The first receiving terminal and the second receiving terminal are electrically coupled to the first signal terminal and the second signal terminal respectively for receiving the unbalanced signals. The subtractor subtracts the noise coming from the first receiving terminal and the noise coming from the second receiving terminal to reduce the output noise of the signal output terminal.
    Type: Application
    Filed: March 15, 2013
    Publication date: May 22, 2014
    Applicant: C-MEDIA ELECTRONICS INC.
    Inventors: WEN-LUNG SHIEH, CHIH-YING HUANG
  • Patent number: 8525571
    Abstract: A voltage amplitude limiting circuit of a full differential circuit is provided for limiting voltage levels of a differential signal. The voltage amplitude limiting circuit includes a reference voltage generating unit and a replacing circuit. The reference voltage generating unit generates a high reference voltage and a low reference voltage. The replacing circuit is coupled to the reference voltage generating unit, a first input terminal and a second input terminal. When voltage at the first input terminal is greater than the high reference voltage, the replacing circuit uses the high reference voltage to replace the voltage at the first input terminal to serve as an output. When voltage at the first input terminal is less than the low reference voltage, the replacing circuit uses the low reference voltage to replace the voltage at the first input terminal to serve as an output.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: September 3, 2013
    Assignee: C-Media Electronics Inc.
    Inventors: Chih Ying Huang, Wen Lung Shieh
  • Publication number: 20120229115
    Abstract: A voltage amplitude limiting circuit of a full differential circuit is provided for limiting voltage levels of a differential signal. The voltage amplitude limiting circuit includes a reference voltage generating unit and a replacing circuit. The reference voltage generating unit generates a high reference voltage and a low reference voltage. The replacing circuit is coupled to the reference voltage generating unit, a first input terminal and a second input terminal. When voltage at the first input terminal is greater than the high reference voltage, the replacing circuit uses the high reference voltage to replace the voltage at the first input terminal to serve as an output. When voltage at the first input terminal is less than the low reference voltage, the replacing circuit uses the low reference voltage to replace the voltage at the first input terminal to serve as an output.
    Type: Application
    Filed: September 8, 2011
    Publication date: September 13, 2012
    Applicant: C-MEDIA ELECTRONICS INC.
    Inventors: CHIH YING HUANG, WEN LUNG SHIEH
  • Patent number: 7053598
    Abstract: The scheme for detecting the plug-in status by using single bit generated by a network with serial resistors, comprising a plurality of jacks having a spring switch, wherein the number of the plurality of jacks can be selected depending on the demand and a plurality of resistors followed the spring switch and connected in serial. Output voltage-generating resistor is coupled to the plurality of resistors in parallel to obtain the output voltage, thereby determining the plug-in status. Wherein the plurality of jacks and the plurality of resistors construct a multi-jack network, a first terminal of the multi-jack network refers to a common node between a first connecting terminals of the spring switch of the plurality of jacks and a first resistor of the plurality of resistors, the first terminal being coupled to a first reference voltage, a second terminal of the multi-Jack network refers to a common node between the second connecting terminals of the last jack and the last resistor.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: May 30, 2006
    Assignee: C-Media Electronics, Inc.
    Inventors: Wen-Lung Shieh, Chih-Hung Tseng
  • Publication number: 20050073453
    Abstract: System of multi-channel shared resistor-string digital-to-analog converters comprises a time-sharing interpolator converting the multi-channel digital audio input at low sample rate to the multi-channel digital audio output at high sample rate, a time-sharing sigma-delta modulator modulating the multi-channel digital audio input with a long sample wordlength from the interpolator to be a multi-channel digital audio output with a shorter sample wordlength, multi-channel shared resistor-string digital-to-analog converters converting the multi-channel digital audio input to be a multi-channel staircase analog signal output, and one low-order RC filter for each channel further attenuating the out-of-band noise in the analog staircase analog output, especially the high-frequency residue images.
    Type: Application
    Filed: October 1, 2003
    Publication date: April 7, 2005
    Inventors: Eric Cheng, Wen-Lung Shieh, Chih-Hung Tseng, Hipolk Lu
  • Patent number: 6870494
    Abstract: System of multi-channel shared resistor-string digital-to-analog converters comprises a time-sharing interpolator converting the multi-channel digital audio input at low sample rate to the multi-channel digital audio output at high sample rate, a time-sharing sigma-delta modulator modulating the multi-channel digital audio input with a long sample wordlength from the interpolator to be a multi-channel digital audio output with a shorter sample wordlength, multi-channel shared resistor-string digital-to-analog converters converting the multi-channel digital audio input to be a multi-channel staircase analog signal output, and one low-order RC filter for each channel further attenuating the out-of-band noise in the analog staircase analog output, especially the high-frequency residue images.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: March 22, 2005
    Assignee: C-Media Electronics Inc.
    Inventors: Eric Cheng, Wen-Lung Shieh, Chih-Hung Tseng, Hipolk Lu
  • Publication number: 20040108845
    Abstract: The scheme for detecting the plug-in status by using single bit generated by a network with serial resistors, comprising a plurality of jacks having a spring switch, wherein the umber of the plurality of jacks can be selected depending on the demand and a plurality of resistors followed the spring switch and connected in serial. Output voltage-generating resistor is coupled to the plurality of resistors in parallel to obtain the output voltage, thereby determining the plug-in status. Wherein the plurality of jacks and the plurality of resistors construct a multi-jack network, a first terminal of the multi-jack network refers to a common node between a first connecting terminals of the spring switch of the plurality of jacks and a first resistor of the plurality of resistors, the first terminal being coupled to a first reference voltage, a second terminal of the multi-Jack network refers to a common node between the second connecting terminals of the last jack and the last resistor.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 10, 2004
    Inventors: Wen-Lung Shieh, Chih-Hung Tseng
  • Publication number: 20040036488
    Abstract: A self-balanced active current bridge for measuring the impedance of an external device or an output current, comprising an input potential source and operation amplifier connected to the input potential source via a first input terminal of the operation amplifier. A balancing bridge is coupled to a first output terminal and a second output terminal of the operation amplifier. A controlled potential source is coupled to the balancing bridge and used to maintain the balance state of the balancing bridge. A resistance is connected between the balancing bridge and an output terminal of the controlled potential source. Wherein the external device is connected a first node between the balancing bridge and a second input terminal of the operation amplifier.
    Type: Application
    Filed: August 27, 2002
    Publication date: February 26, 2004
    Inventors: Wen-Lung Shieh, Chih-Hung Tseng
  • Patent number: 6696846
    Abstract: A self-balanced active current bridge for measuring the impedance of an external device or an output current, including an input potential source and operation amplifier connected to the input potential source via a first input terminal of the operation amplifier. A balancing bridge is coupled to a first output terminal and a second output terminal of the operation amplifier. A controlled potential source is coupled to the balancing bridge and used to maintain the balance state of the balancing bridge. A resistance is connected between the balancing bridge and an output terminal of the controlled potential source. Wherein the external device is connected a first node between the balancing bridge and a second input terminal of the operation amplifier.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: February 24, 2004
    Assignee: C-Media Electronics Inc.
    Inventors: Wen-Lung Shieh, Chih-Hung Tseng