Abstract: A parallel hardware searching device (PHSD) is used to build an artificial intelligent computer, wherein the system mainly contains a hardware search module and several DRAM (or universal memory) modules, said hardware search module comprises: a processing unit (PU) architecture contains mainly a comparator and controller, m PUs which are connected with m BRAM units and one Inter Processing Unit Logic, PU only process the data in its own BRAM unit, PUs are also connected to Inter Processing Unit Logic (IPUL) which processes the functions between PUs; a PCIE interface controller which is used to connect search module to external PC, search module use PCIE to receive data or command from PC, or transmit data to PC; a PHDS includes a controller which is used to execute 5 commands: Search, Insertion, Deletion, Load to BRAM and Store to DRAM.

Abstract: An affordable artificial intelligent (AI) computer is invented by combining present computer with a parallel hardware search system. Such a computer can be treated as a Turing Machine. Instead of sequentially processing computer instructions, this computer executes AI logic reasoning. The parallel hardware search system use pure parallel hardware to execute virtual B-tree search. Hierarchical page table and hash techniques are also used for very large data volume. The prototype of this invented system is successfully built into a PCIE card which mainly contains a Xilinx's Kintex7 FPGA chip and two DDR3 memory modules. FPGA chip includes: 32 32-bit processing units (PUs), one PCIE controller, one search/delete/insert controller and two DDR3 controllers.

Abstract: An affordable artificial intelligent (AI) computer is invented by combining present computer with a parallel hardware search system. Such a computer can be treated as a Turing Machine. Instead of sequentially processing computer instructions, this computer executes AI logic reasoning The parallel hardware search system use pure parallel hardware to execute virtual B-tree search. Hierarchical page table and hash techniques are also used for very large data volume. The prototype of this invented system is successfully built into a PCIE card which mainly contains a Xilinx's Kintex7 FPGA chip and two DDR3 memory modules. FPGA chip includes: 32 32-bit processing units (PUs), one PCIE controller, one search/delete/insert controller and two DDR3 controllers.

Abstract: The present invention relates to a method of implementing B++ tree search on parallel for virtual tree searcher, in which there is no need to construct and maintain tree structure. In each search step, all processor units (PUs) can be involved to complete search operation. Such kind of searcher can be implemented on hardware with low developing and production cost.

Abstract: The present invention relates to a method of implementing B++ tree search on parallel for virtual tree searcher, in which there is no need to construct and maintain tree structure. In each search step, all processor units (PUs) can be involved to complete search operation. Such kind of searcher can be implemented on hardware with low developing and production cost.