Abstract: Apparatuses, systems, and techniques to use parallel processing unit(s) (“PPU(s)”) to perform data access(es) in response to data access request(es). The data access(es) may be performed by accessing at least a first portion of data stored in at least a first location of data location(s) if the first location is on a first tier of a plurality of data tiers that is accessible by the PPU(s), and causing server interface(s) to access at least a second portion of the data stored in at least a second location of the data location(s) if the second location is on a second tier of the plurality of data tiers. The data access request(s) may be performed using an API. The data access(es) may be performed by client(s) and the server interface(s) may be implemented by server(s). The client(s) and server(s) may be implemented by node(s), and may be paused and migrated to other node(s) during execution time. The client(s) may implement synchronous and/or asynchronous interfaces.

Abstract: A computer-implemented method for generating an abstract meaning representation (“AMR”) of a sentence, comprising receiving, by a computing device, an input sentence and parsing the input sentence into one or more syntactic and/or semantic graphs. An input graph including a node set and an edge set is formed from the one or more syntactic and/or semantic graphs. Node representations are generated by natural language processing. The input graph is provided to a first neural network to provide an output graph having learned node representations aligned with the node representations in the input graph. The method further includes predicting via a second neural network, node label and predicting, via a third neural network, edge labels in the output graph. The AMR is generated based on the predicted node labels and predicted edge labels. A system and a non-transitory computer readable storage medium are also disclosed.

Abstract: A computer-implemented method for generating an abstract meaning representation (“AMR”) of a sentence, comprising receiving, by a computing device, an input sentence and parsing the input sentence into one or more syntactic and/or semantic graphs. An input graph including a node set and an edge set is formed from the one or more syntactic and/or semantic graphs. Node representations are generated by natural language processing. The input graph is provided to a first neural network to provide an output graph having learned node representations aligned with the node representations in the input graph. The method further includes predicting via a second neural network, node label and predicting, via a third neural network, edge labels in the output graph. The AMR is generated based on the predicted node labels and predicted edge labels. A system and a non-transitory computer readable storage medium are also disclosed.

Abstract: A computer-implemented method is provided for transferring a target text style using Reinforcement Learning (RL). The method includes pre-determining, by a Long Short-Term Memory (LSTM) Neural Network (NN), the target text style of a target-style natural language sentence. The method further includes transforming, by a hardware processor using the LSTM NN, a source-style natural language sentence into the target-style natural language sentence that maintains the target text style of the target-style natural language sentence. The method also includes calculating an accuracy rating of a transformation of the source-style natural language sentence into the target-style natural language sentence based upon rewards relating to at least the target text style of the source-style natural language sentence.

Abstract: A computer-implemented method is provided for transferring a target text style using Reinforcement Learning (RL). The method includes pre-determining, by a Long Short-Term Memory (LSTM) Neural Network (NN), the target text style of a target-style natural language sentence. The method further includes transforming, by a hardware processor using the LSTM NN, a source-style natural language sentence into the target-style natural language sentence that maintains the target text style of the target-style natural language sentence. The method also includes calculating an accuracy rating of a transformation of the source-style natural language sentence into the target-style natural language sentence based upon rewards relating to at least the target text style of the source-style natural language sentence.

Abstract: Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

Abstract: Embodiments for providing direct access to non-volatile memory by a processor. One or more accelerators may be provided, via an application programming interface (“API”), direct access to non-volatile storage independent of a host central processing unit (“CPU”) on a control path or data path to perform a read operation and write operation of data.

Abstract: Embodiments for providing direct access to non-volatile memory by a processor. One or more accelerators may be provided, via an application programming interface (“API”), direct access to non-volatile storage independent of a host central processing unit (“CPU”) on a control path or data path to perform a read operation and write operation of data.

Abstract: Various embodiments are provided for providing byte granularity accessibility of memory in a unified memory-storage hierarchy in a computing system by a processor. A location of one or more secondary memory medium pages in a secondary memory medium may be mapped into an address space of a primary memory medium to extend a memory-storage hierarchy of the secondary memory medium. The one or more secondary memory medium pages may be promoted from the secondary memory medium to the primary memory medium. The primary memory medium functions as a cache to provide byte level accessibility to the one or more primary memory medium pages. A memory request for the secondary memory medium page may be redirected using a promotion look-aside buffer (“PLB”) in a host bridge associated with the primary memory medium and the secondary memory medium.

Abstract: A processor triggers a first advanced execution processing pass to an instruction sequence in response to a stalled instruction and initiates execution of a further instruction in the instruction sequence that stalls during the performance of the first advance execution processing pass. A second advance execution pass is performed through the instruction sequence in which the second instruction is processed again to provide a valid result after stalling that is used to perform one or more other instructions in the instruction sequence. In one form, the first instruction is performed while the processor operates in a normal execution mode and the first and second advance execution processing passes are performed while the processor operates in an advance execution mode.

Abstract: In compiling a program, the present algorithm first analyzes each function in the program as an isolated compilation unit where parameters and global variables are temporarily assumed to have uninitialized values. This stage of the algorithm, the intraprocedural phase, will summarize the intraprocedural behavior of a function in a flow-insensitive manner, including how it can affect memory accesses in the caller and callee functions, and how its memory accesses can be affected by the caller and callee functions. The summarized behavior of each function is the only information to be processed in the next stage, the interprocedural stage. A significant size reduction is achieved in the summarized representation as compared to the full function body. This facilitates aggressive optimization of even large programs.

Abstract: The invention is a method for debugging a machine code of a program that has been subjected to an optimizing action, wherein the machine code may have been reordered, duplicated, eliminated or transformed so as not to correspond with the program's source code order. The method derives a table which associates each machine code instruction with a source construct for which it was generated. The user sets a breakpoint at a breakpoint P in the source code where execution is to stop. Then the method determines at least one corresponding location for the breakpoint in the machine code through use of the table, and executes by native execution or emulation only machine code instructions which correspond to source constructs that precede the breakpoint in the source code order.