Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.

Abstract: A pipe connector in accordance with the present invention comprises a hollow body, a rotator rotatably and co-axially sleeved on one end of the hollow body, a positioning device co-axially mounted between the hollow body and the rotator, and a holder co-axially mounted to rotator for holding the positioning device in place in the rotator. The positioning device includes a bind ring that is pre-expanded by an opener. The pipe is tightly bound to airtightly abut against the hollow body due to the restitution force of the bind ring when the pipe pushes the opener to make the opener detaching from the bind ring.

Abstract: A metal etching process. A glue/barrier layer, a metal layer and an anti-refeletion layer are formed on a substrate. A three-stage etching step is performed. A break through step of etching is performed to pattern the glue/barrier layer. A main etching step is performed on the metal layer with chlorine, boron trichloride, and trifluoro-methane as etching gases. The trifluoro-methane is advantageous to produce a polymer during etching, so that the profile of the metal layer appears atilt. An over-etching step is then performed to ensure an insulation between neighboring wiring lines.

Abstract: A metal etching process. A glue/barrier layer, a metal layer and an anti-refeletion layer are formed on a substrate. A three-stage etching step is performed. A break through step of etching is performed to pattern the glue/barrier layer. A main etching step is performed on the metal layer with chlorine, boron trichloride, and trifluoro-methane as etching gases. The trifluoro-methane is advantageous to produce a polymer during etching, so that the profile of the metal layer appears atilt. An over-etching step is then performed to ensure an insulation between neighboring wiring lines.

Abstract: A method mending the erosion of bonding pad. A passivation layer and a polyimide layer are sequentially formed on a wafer to cover a bonding pad, where the polyimide layer is patterned to expose a portion of the passivation layer. The polyimide layer is used as a mask for etching the passivation layer, so as to expose the bonding pad. The bonding pad is eroded by the etchant residue remaining after etching the passivation layer on the bonding pad. After removing the eroded part of the bonding pad, an oxide layer is formed subsequently to prevent a further erosion.

Abstract: An improved method of forming a conductive line on a semiconductor substrate is described. A conductive layer is formed on the substrate. A patterned photoresist layer is formed on the conductive layer. A first etching step is performed on the conductive layer to define the conductive layer and to form a conductive line. A second etching step is performed on the conductive line to undercut the conductive line so as to make the conductive line have smaller bottom and to increase a distance between neighboring conductive lines. A third etching step is performed to remove residue generated on the substrate during the first and the second etching steps. A dielectric layer is formed to cover the conductive line. A planarization process is performed.