Patents by Inventor Wen-Pin Peng
Wen-Pin Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10854472Abstract: Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.Type: GrantFiled: March 19, 2014Date of Patent: December 1, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Huang Liu, Wen-Pin Peng, Jean-Baptiste Laloe
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Patent number: 10290634Abstract: A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second fins coupled to the semiconductor substrate having a second fin pitch larger than the first fin pitch. The semiconductor structure further includes transistor(s) on the multiple first fins, and transistor(s) on the multiple second fins, a threshold voltage of the transistor(s) on the multiple second fins being higher than that of the transistor(s) on the multiple first fins.Type: GrantFiled: January 20, 2016Date of Patent: May 14, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Wen Pin Peng, Min-hwa Chi
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Patent number: 9905673Abstract: Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.Type: GrantFiled: June 12, 2017Date of Patent: February 27, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Wen-Pin Peng, Min-hwa Chi
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Publication number: 20170278949Abstract: Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.Type: ApplicationFiled: June 12, 2017Publication date: September 28, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Wen-Pin PENG, Min-hwa CHI
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Publication number: 20170207118Abstract: A starting semiconductor structure for a RMG process includes a semiconductor substrate, transistors in process having dummy gates and electrically isolated by isolation regions. The dummy gates are replaced with metal gates and gate caps, the structure being planarized after replacing the gate. A cap layer is formed over the planarized structure, and trenches are formed through the cap to expose source and drain regions of the transistors, which allows for self-aligned source and drain contacts. Semiconductor structures including the source and drain trenches for self-aligned source/drain contacts are also presented.Type: ApplicationFiled: January 14, 2016Publication date: July 20, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Wen Pin PENG, Min-hwa CHI, Yue HU
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Publication number: 20170207090Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.Type: ApplicationFiled: January 19, 2016Publication date: July 20, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Wen-Pin PENG, Min-hwa CHI
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Publication number: 20170207216Abstract: A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second fins coupled to the semiconductor substrate having a second fin pitch larger than the first fin pitch. The semiconductor structure further includes transistor(s) on the multiple first fins, and transistor(s) on the multiple second fins, a threshold voltage of the transistor(s) on the multiple second fins being higher than that of the transistor(s) on the multiple first fins.Type: ApplicationFiled: January 20, 2016Publication date: July 20, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Wen Pin PENG, Min-hwa CHI
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Patent number: 9711619Abstract: In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.Type: GrantFiled: January 19, 2016Date of Patent: July 18, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Wen-Pin Peng, Min-hwa Chi
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Patent number: 9704759Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.Type: GrantFiled: September 4, 2015Date of Patent: July 11, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
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Patent number: 9607989Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.Type: GrantFiled: December 4, 2014Date of Patent: March 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xusheng Wu, Yue Hu, Xin Wang, Yong Meng Lee, Wen-Pin Peng, Lun Zhao, Wei-Hua Tong
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Publication number: 20170069547Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.Type: ApplicationFiled: September 4, 2015Publication date: March 9, 2017Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
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Patent number: 9396995Abstract: A method of forming a metalized contact in MOL is provided. Embodiments include forming a TT through an ILD down to a S/D region; forming a SiOC, SiCN, or SiON layer on side surfaces of the TT; performing a GCIB vertical etching at a 0° angle; implanting Si into the TT by an angled PAI; removing a portion of the TT by Ar sputtering and a remote plasma assisted dry etch process; forming NiSi on the S/D region at the bottom of the TT; and filling the TT with contact metal over the NiSi.Type: GrantFiled: February 27, 2015Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Suraj K. Patil, Min-hwa Chi, Garo Derderian, Wen-Pin Peng
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Patent number: 9385124Abstract: One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.Type: GrantFiled: September 4, 2015Date of Patent: July 5, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Wen Pin Peng, Min-hwa Chi, Garo Jacques Derderian
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Patent number: 9385030Abstract: Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be etched partway to a source-drain region of the semiconductor device. A dielectric liner can be deposited in this trench. A second etch can be performed on the lined trench to etch the contact trench channel the remainder of the way to the source-drain region. This leaves a portion of the dielectric liner remaining in the trench (e.g., covering the vertical walls of the trench) after the second etch.Type: GrantFiled: April 30, 2014Date of Patent: July 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Yong M. Lee, Yue Hu, Wen-Pin Peng
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Publication number: 20160163702Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed.Type: ApplicationFiled: December 4, 2014Publication date: June 9, 2016Inventors: Xusheng WU, Yue HU, Xin WANG, Yong Meng LEE, Wen-Pin PENG, Lun ZHAO, Wei-Hua TONG
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Patent number: 9184288Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.Type: GrantFiled: March 13, 2014Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Sipeng Gu, Zhiguo Sun, Sandeep Gaan, Danni Chen, Wen-Pin Peng, Huang Liu
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Publication number: 20150318204Abstract: Aspects of the present invention relate to approaches for preventing contact encroachment in a semiconductor device. A first portion of a contact trench can be etched partway to a source-drain region of the semiconductor device. A dielectric liner can be deposited in this trench. A second etch can be performed on the lined trench to etch the contact trench channel the remainder of the way to the source-drain region. This leaves a portion of the dielectric liner remaining in the trench (e.g., covering the vertical walls of the trench) after the second etch.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Yong M. Lee, Yue Hu, Wen-Pin Peng
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Publication number: 20150270142Abstract: Aspects of the present invention relate to approaches for forming a semiconductor device such as a field-effect-transistor (FET) having a metal gate with improved performance. A metal gate is formed on a substrate in the semiconductor device. Further processing can result in unwanted oxidation in the metal that forms the metal gate. A reducing agent can be used to de-oxidize the metal that forms the metal gate, leaving a substantially non-oxidized surface.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Huang Liu, Wen-Pin Peng, Jean-Baptiste Laloe
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Publication number: 20150263169Abstract: Semiconductor structures and fabrication methods are provided having a bridging film which facilitates adherence of both an underlying layer of dielectric material and an overlying stress-inducing layer. The method includes, for instance, providing a layer of dielectric material, with at least one gate structure disposed therein, over a semiconductor substrate; providing a bridging film over the layer of dielectric material with the at least one gate structure; and providing a stress-inducing layer over the bridging film. The bridging film is selected to facilitate adherence of both the underlying layer of dielectric material and the overlying stress-inducing layer by, in part, forming a chemical bond with the layer of dielectric material, without forming a chemical bond with the stress-inducing layer.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Sipeng GU, Zhiguo SUN, Sandeep GAAN, Danni CHEN, Wen-Pin PENG, Huang LIU
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Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection
Patent number: 9123783Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.Type: GrantFiled: November 9, 2012Date of Patent: September 1, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Xin Wang, Changyong Xiao, Yue Hu, Yong Meng Lee, Meng Luo, Jialin Weng, Wei Hua Tong, Wen-Pin Peng