Abstract: A method for detecting defects on a wafer including the steps of obtaining a reference image of a chip pattern formed on a reference wafer, using a computer algorithm to analyze the reference image to produce a division map for the chip pattern; setting respective thresholds for divisions of the division map, obtaining a comparison data between a test image of the chip pattern formed on a test wafer and the reference image, using the division map and the thresholds to examine the comparison data to identify a defect in the test image.

Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

Abstract: An elastic assembly structure for a bicycle pedal includes a pedal, a sole cleat and an elastic element. The elastic element is removably connected between the pedal and the sole cleat by a magnet. In riding a bicycle, the pedal and the sole cleat are expanded and collected with each other elastically, and a user's leg can lift up and put down a rear edge of the sole spontaneously following a circumferential stepping movement, and the rear end of the sole cleat can lift up and drive the rear end of the pedal elastically through the elastic element. Accordingly, the user can stop the bicycle, get off the bicycle or brake the bicycle emergently, simply by lifting up the leg spontaneously to overcome the magnetic force of the magnet, allowing the sole cleat to escape from the pedal rapidly, thereby improving the smoothness and safety in riding the bicycle.

Abstract: In the Flip-Chip type LED component built therein with a Zener chip: a Flip-Chip LED chip and a Flip-Chip Zener straddle respectively over and beneath two electrode pins, wherein the Flip-Chip Zener is covered with insulating material to form a base and the Flip-Chip LED chip is covered with a transparent package to thereby form an integral Flip-Chip LED component, hence not only the Flip-Chip LED component can be protected in use, but also can largely simplify the production process and reduce the cost of production.

Abstract: A well-through type diode element/component manufacturing method which has a pair (pairs) of first and said second electrodes of a diode element/component built on same plane by a process of metallization after a mode of well-through type to penetrate a PN junction depletion region/barrier region, and leads electrons of one of the electrodes to flow through the Depletion/Barrier region without hindrance; the present invention directly conduct the operations of insulation protecting, metallization and the process of elongate welding ball etc., it can independently complete a novel technique of Chip-Scale Package (CSP); it has the features of: grains being exactly the article produced, no need of connecting lines, low energy consumption, low cost and light, thin and small etc.

Abstract: This invention reveals a constant current semiconductor device of an N-type or a P-type epitaxial layer on a semi-insulating substrate, the device is treated by using a Schottky barrier to cut off current in conduction channels under certain bias and to provide constant current within cut-off voltage and breakdown voltage region between Schottky barrier section/ohmic contact section as the first electrode and the other ohmic contact section as the second electrode respectively, and has excellent characteristics as lower cut-off voltage (Vkp) than bipolar devices and easily gets higher constant current (Ip) by integrating several constant current units.

Abstract: A method for processing power-off suitable for a server system is provided. The server system includes a first node, a second node, and a power supply. The first and second nodes share the power supply. The method includes the following steps. A power-off process is performed by the first and second nodes respectively according to a power-off signal. An interception process is activated to intercept a completion signal generated in the power-off process, and an interrupt is triggered. The interrupt is performed by an interrupt handler, so as to detect whether the first and second nodes complete a power-off process. When the first and second nodes already complete the power-off process, the interception process is inactivated and the generated completion signal is recovered and transferred to the power supply for turning off a power.

Abstract: A well-through type diode element/component manufacturing method which has a pair (pairs) of first and said second electrodes of a diode element/component built on same plane by a process of metallization after a mode of well-through type to penetrate a PN junction depletion region/barrier region, and leads electrons of one of the electrodes to flow through the Depletion/Barrier region without hindrance; the present invention directly conduct the operations of insulation protecting, metallization and the process of elongate welding ball etc., it can independently complete a novel technique of Chip-Scale Package (CSP); it has the features of: grains being exactly the article produced, no need of connecting lines, low energy consumption, low cost and light, thin and small etc.

Abstract: This invention reveals a flip-chip type full-wave rectification semiconductor device which includes at least a PNNP type and/or NPPN type flip-chip, and a sheet stuff or substrate including a plurality pins, and which is characterized in that: all the soldering points (bumps) of the PNNP type and/or the NPPN type flip-chip are on an identical surface, this can make easy connecting of the pins with the bumps of the flip-chips by soldering in pursuance of circuit arrangement of the full-wave rectification device, and complete manufacturing product after the steps of shaping/packing and cutting; such product has a function of making full-wave rectifying, and can simplify the manufacturing process, reduce the manufacturing cost, and get an effect of reducing the size of the product with better heat dissipation, being different from traditional full wave rectification semiconductor devices composed of two/four grains.

Abstract: A manufacturing method and a structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate, in the method, a diffused wafer is stacked with a high temperature durable high strength base plate to have them sintered and molten together for connecting with each other to form a co-constructure; then the diffused wafer is processed by etching and ditching for filling with insulation material, electrodes of the diffused wafer are metalized and all on an identical plane, then production of all functional lines is completed; and then the co-constructure is cut to form a plurality of separated individuals which each forms a surface-mounting type diode to be applied straight. In comparison with the conventional techniques, manufacturing of the present invention is simplified and economic in reducing working hours, size and cost of production and the wafer is not subjected to breaking during manufacturing.

Abstract: This invention reveals a constant current semiconductor device of an N-type or a P-type epitaxial layer on a semi-insulating substrate, the device is treated by using a Schottky barrier to cut off current in conduction channels under certain bias and to provide constant current within cut-off voltage and breakdown voltage region between Schottky barrier section/ohmic contact section as the first electrode and the other ohmic contact section as the second electrode respectively, and has excellent characteristics as lower cut-off voltage (Vkp) than bipolar devices and easily gets higher constant current (Ip) by integrating several constant current units.

Abstract: A method for processing power-off suitable for a server system is provided. The server system includes a first node, a second node, and a power supply. The first and second nodes share the power supply. The method includes the following steps. A power-off process is performed by the first and second nodes respectively according to a power-off signal. An interception process is activated to intercept a completion signal generated in the power-off process, and an interrupt is triggered. The interrupt is performed by an interrupt handler, so as to detect whether the first and second nodes complete a power-off process. When the first and second nodes already complete the power-off process, the interception process is inactivated and the generated completion signal is recovered and transferred to the power supply for turning off a power.

Abstract: A manufacturing method and a structure of a surface-mounting type diode co-constructed from a silicon wafer and a base plate, in the method, a diffused wafer is stacked with a high temperature durable high strength base plate to have them sintered and molten together for connecting with each other to form a co-constructure; then the diffused wafer is processed by etching and ditching for filling with insulation material, electrodes of the diffused wafer are metalized and all on an identical plane, then production of all functional lines is completed; and then the co-constructure is cut to form a plurality of separated individuals which each forms a surface-mounting type diode to be applied straight. In comparison with the conventional techniques, manufacturing of the present invention is simplified and economic in reducing working hours, size and cost of production and the wafer is not subjected to breaking during manufacturing.

Abstract: A basic input/output system (BIOS) capable of supporting multi-platforms and a constructing method thereof are provided. In the method, a plurality of segment modules is provided, and each of the segment modules includes more than one BIOS module. A module header is established for each of the BIOS modules and records an application platform identifier (ID) of an applicable platform of the corresponding BIOS module and module type data of the corresponding BIOS module. The segment modules are then integrated according to a design structure of the BIOS. The segment modules are classified into a main system module, a plurality of slave segment modules, and a reset entry segment module. When the reset entry segment module obtains a platform ID of an electronic equipment currently configured with the BIOS, the main system module pre-stores an execution sequence according to the platform ID, and sequentially runs the BIOS modules matching with the platform ID.

Abstract: A computer system and a method for a configuration management program transmitting a system information are provided. The method includes the following steps. A first memory is provided, wherein the first memory records at least one system information. An interrupt is enabled from the configuration management program when the configuration management program needs a system information of the computer system, wherein the interrupt has a corresponding command information. An interrupt processing program processes the interrupt so as to perform a corresponding configuration setting operation according to the command information or to return the corresponding system information in the first memory to the configuration management program.

Abstract: A designing for a power semiconductor, and especially to a structure of a power semiconductor formed by using the basic materials including two metal plates and a ceramic plate, in the power semiconductor, mainly surfaces of the ceramic base plate provided with a receiving groove is metallized, and the metallic base plates having electric connecting pins extending outwards therefrom are placed at the two lateral sides of the ceramic base plate, then a chip is placed in the receiving groove of the ceramic base plate, and the ceramic base plate is sintered together with the two metallic base plates, thus the structure of the power semiconductor with the twin metal plates and the ceramic plate is formed.

Abstract: A designing for a power semiconductor, and especially to a structure of a power semiconductor formed by using the basic materials including two metal plates and a ceramic plate, in the power semiconductor, mainly surfaces of the ceramic base plate provided with a receiving groove is metallized, and the metallic base plates having electric connecting pins extending outwards therefrom are placed at the two lateral sides of the ceramic base plate, then a chip is placed in the receiving groove of the ceramic base plate, and the ceramic base plate is sintered together with the two metallic base plates, thus the structure of the power semiconductor with the twin metal plates and the ceramic plate is formed.

Abstract: The heat sinking structure of the present invention is fixedly provided on the surface of a crystal layer of a semiconductor with a heat conducting plate made of copper, the heat conducting plate has therein a plurality of channels parallel to the surface of the crystal layer, the channels extend through the heat conducting plate to form passageways for guiding air flow to exhaust, and to speed up the heat exchanging of the heat conducting plate with air, so that a heat sinking structure that is structurally firm, small by volume and high in efficiency of heat sinking as well as easy for processing in manufacturing is obtained.