Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.

Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.

Abstract: A semiconductor device includes a substrate, a conductive material, and a material layer. The substrate includes a through hole. The conductive material fills the through hole. The material layer is formed in the conductive material, wherein an electrical resistance of the conductive material is lower than an electrical resistance of the material layer.

Abstract: A semiconductor device is disclosed, including a substrate, a fin type semiconductor layer disposed on the substrate, a gate dielectric layer disposed on a top and sidewalls of the fin type semiconductor layer, a metal nitride layer disposed on the gate dielectric layer, and an aluminum doped metal nitride layer disposed on the metal nitride layer. In an embodiment of the invention, the metal nitride layer is a titanium nitride layer and the aluminum doped metal nitride layer is an aluminum doped titanium nitride layer.

Abstract: An interconnection structure includes a lower layer metal wire in a first inter-metal dielectric layer on a substrate; a second inter-metal dielectric layer on the first inter-metal dielectric layer and covering the lower layer metal wire; an upper layer metal wire on the second inter-metal dielectric layer; and a via interconnection structure in the second inter-metal dielectric layer for interconnecting the upper layer metal wire with the lower layer metal wire, wherein the via interconnection structure comprises a tungsten stud on the lower layer metal wire, and an aluminum plug stacked on the tungsten stud.

Abstract: A method for measuring a thin film thickness is provided. The method includes the following steps: providing a plurality of structures, each including a semiconductor substrate, a thin film, and a metal layer; measuring resistances of the metal layers of the plurality of structures and thicknesses of the thin films of the plurality of structures to obtain a plurality of resistance values and a plurality of corresponding thickness values; establishing a thickness-resistance table based on the plurality of resistance values and thickness values; providing a structure to be tested including a semiconductor substrate, a thin film, and a metal layer; and measuring resistance of the metal layer of the structure to be tested to determine a thickness value of the thin film of the structure to be tested according to the thickness-resistance table.