Patents by Inventor Wen-Ping Yen

Wen-Ping Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070066055
    Abstract: A method of fabricating a patterned conductive layer is provided. First, a conductive layer whose material includes at least aluminum-copper (Al—Cu) alloy is formed on a substrate. Then, a heat treatment process is performed to heat the conductive layer to a temperature higher than the phase change temperature of the Al—Cu alloy. Next, the conductive layer is patterned. The method in the present invention can avoid the formation of metallic educt and facilitate subsequent etching processes.
    Type: Application
    Filed: September 20, 2005
    Publication date: March 22, 2007
    Inventors: Chien-Hsin Huang, Wen-Ping Yen
  • Publication number: 20070054490
    Abstract: A semiconductor process for preventing the layer on a wafer edge from peeling is provided. First, a dielectric layer is formed on the front side of a substrate. Then, a photoresist layer is formed to cover the front side and part of the backside of the substrate. Thereafter, an edge rinsing process is carried out only on the backside of the substrate to remove the photoresist layer on the back of the substrate while retaining the photoresist layer on the wafer edge area.
    Type: Application
    Filed: September 2, 2005
    Publication date: March 8, 2007
    Inventors: Yen-Hung Chen, Wen-Ping Yen, Su-Ling Tseng
  • Publication number: 20030146478
    Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.
    Type: Application
    Filed: March 7, 2003
    Publication date: August 7, 2003
    Applicant: SILICON INTEGRATED SYSTEMS CORP.
    Inventors: Wen Ping Yen, Yun Hsiu Chen, Hung-Cheng Weng
  • Patent number: 6551883
    Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: April 22, 2003
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Wen Ping Yen, Yun Hsiu Chen, Hung-Cheng Weng
  • Patent number: 6171764
    Abstract: This invention provides methods for reducing the intensity of reflected rays encountered during the process of photolithography. By reducing the intensity of reflected ray, the pattern distortions associated with the interference from secondary rays can be minimized. In addition, this method for reducing the intensity of reflected ray can also eliminate the footing effect of other known methods in which the dielectric ARC layer is first deposited on the underlying layer, followed by the subsequent photolithography process of coating exposing, and developing.
    Type: Grant
    Filed: August 22, 1998
    Date of Patent: January 9, 2001
    Inventors: Chia-Lin Ku, Wen-Ping Yen
  • Patent number: 6156597
    Abstract: A method of fabricating a semiconductor device is provided including the steps of:(a) forming one or more protrusions on a semiconductor surface,(b) forming a first O.sub.x /TEOS film on top and side surfaces of the protrusions and surface area portions of the semiconductor surface separating the protrusions from each other, if any, and(c) forming a second O.sub.3 /TEOS film on, and covering, the first film.Illustratively, the protrusions have nitride regions at their peaks. The first film can be a low pressure (e.g., 30-70 torr) O.sub.3 /TEOS film or a plasma enhanced chemical vapor deposition (PECVD) O.sub.2 /TEOS film. The second film is a high pressure (e.g., 200-600 torr) O.sub.3 /TEOS film.The high pressure O.sub.3 /TEOS film avoids all of the disadvantages of the prior art. The low pressure O.sub.3 /TEOS film or PECVD O.sub.2 /TEOS film covers the nitride region of the protrusion so that the high pressure O.sub.3 /TEOS film will continuously cover the entire structure with a uniform thickness.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: December 5, 2000
    Assignees: ProMOS Technologies, Inc., Mosel Vitelic, Inc., Siemens AG
    Inventors: Wen-Ping Yen, Chia-Lin Ku, Chong-Che Lee
  • Patent number: 5868843
    Abstract: A detachable sponge device for a spin coating machine used to coat a liquid material over a semiconductor wafer is provided. The detachable sponge device is used to prevent the solvent that is jetted on the edge of the wafer from being oversprayed elsewhere on the wafer. The detachable sponge device is composed of a curved mounting piece and a corrugated piece of sponge attached on the curved inner side of the mounting piece. The mounting piece can be detachably mounted on the spin coating machine. The corrugated piece of sponge can absorb splattered particles of solvent from the wafer which can thus be prevented from bouncing back onto the wafer. The planarization of the coating of SOG on the wafer thus will not be affected by splattering particles of the solvent. Excellent results of planarization of SOG or photoresist layers can thus be achieved.
    Type: Grant
    Filed: January 14, 1997
    Date of Patent: February 9, 1999
    Assignee: Winbond Electronics Corporation
    Inventors: Yu-Chen Yang, Chang-Chi Huang, Wen-Ping Yen