Patents by Inventor Wen-Sheh Huang
Wen-Sheh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210257295Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a low-k dielectric layer over the second dielectric layer, a second dielectric layer on the high resistance layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.Type: ApplicationFiled: June 19, 2020Publication date: August 19, 2021Inventors: Hong-Wei Chan, Yung-Shih Cheng, Wen-Sheh Huang, Yu-Hsiang Chen
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Publication number: 20210257293Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.Type: ApplicationFiled: October 14, 2020Publication date: August 19, 2021Inventors: Hui Lee, Po-Hsiang Huang, Wen-Sheh Huang, Jen Hung Wang, Su-Jen Sung, Chih-Chien Chi, Pei-Hsuan Lee
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Publication number: 20210257296Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.Type: ApplicationFiled: December 3, 2020Publication date: August 19, 2021Inventors: Hong-Wei CHAN, Yung-Shih CHENG, Wen-Sheh HUANG
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Publication number: 20210249251Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.Type: ApplicationFiled: March 31, 2021Publication date: August 12, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiu-Wen HSUEH, Yu-Hsiang CHEN, Wen-Sheh HUANG, Chii-Ping CHEN, Wan-Te CHEN
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Patent number: 10985011Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.Type: GrantFiled: January 9, 2018Date of Patent: April 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiu-Wen Hsueh, Yu-Hsiang Chen, Wen-Sheh Huang, Chii-Ping Chen, Wan-Te Chen
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Publication number: 20200118876Abstract: A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a conductive line in the dielectric layer. The method also includes forming an etch stop layer over the dielectric layer and the conductive line and patterning the etch stop layer to form a contact opening exposing a portion of the conductive line. The method further includes forming a resistive layer over the etch stop layer, wherein the resistive layer extends into the contact opening. In addition, the method includes patterning the resistive layer to form a resistive element.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Sheh HUANG, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
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Patent number: 10515852Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element electrically connected to the conductive feature. A first portion of the resistive element is over the dielectric layer, and a second portion of the resistive element extends towards the conductive feature.Type: GrantFiled: January 9, 2018Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Sheh Huang, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
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Publication number: 20190279933Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. The thermal conductive element at least partially overlaps the resistive element. In addition, the semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
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Patent number: 10304772Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.Type: GrantFiled: May 19, 2017Date of Patent: May 28, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wan-Te Chen, Chung-Hui Chen, Wei-Chih Chen, Chii-Ping Chen, Wen-Sheh Huang, Bi-Ling Lin, Sheng-Feng Liu
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Publication number: 20190139826Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element electrically connected to the conductive feature. A first portion of the resistive element is over the dielectric layer, and a second portion of the resistive element extends towards the conductive feature.Type: ApplicationFiled: January 9, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Sheh HUANG, Hsiu-Wen HSUEH, Yu-Hsiang CHEN, Chii-Ping CHEN
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Publication number: 20190139754Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.Type: ApplicationFiled: January 9, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiu-Wen HSUEH, Yu-Hsiang CHEN, Wen-Sheh HUANG, Chii-Ping CHEN, Wan-Te CHEN
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Patent number: 10164002Abstract: A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers.Type: GrantFiled: February 16, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wan-Te Chen, Chung-Hui Chen, Chii-Ping Chen, Chung-Yi Lin, Wen-Sheh Huang
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Publication number: 20180337125Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a gate stack, and an interconnect structure over the gate stack and the semiconductor substrate. The semiconductor device structure also includes a resistive element over the interconnect structure, and the resistive element is directly above the gate stack. The semiconductor device structure further includes a thermal conductive element over the interconnect structure. A direct projection of the thermal conductive element on a main surface of the resistive element extends across a portion of a first imaginary line and a portion of a second imaginary line of the main surface. The first imaginary line is perpendicular to the second imaginary line. The first imaginary line and the second imaginary line intersect at a center of the main surface. The semiconductor device structure includes a dielectric layer separating the thermal conductive element from the resistive element.Type: ApplicationFiled: May 19, 2017Publication date: November 22, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Te CHEN, Chung-Hui CHEN, Wei-Chih CHEN, Chii-Ping CHEN, Wen-Sheh HUANG, Bi-Ling LIN, Sheng-Feng LIU
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Publication number: 20180151665Abstract: A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers.Type: ApplicationFiled: February 16, 2017Publication date: May 31, 2018Inventors: WAN-TE CHEN, CHUNG-HUI CHEN, CHII-PING CHEN, CHUNG-YI LIN, WEN-SHEH HUANG
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Patent number: 9147020Abstract: A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length.Type: GrantFiled: April 21, 2011Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Ying Cho, Jiun-Kai Huang, Wen-Sheh Huang, Chin-Wei Kuo, Min-Chie Jeng
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Patent number: 8796095Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.Type: GrantFiled: September 22, 2011Date of Patent: August 5, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Pin Lin, Wen-Sheh Huang, Tian-Choy Gan, Chia-Lung Hung, Hsien-Chin Lin, Shyue-Shyh Lin
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Patent number: 8557692Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region.Type: GrantFiled: January 12, 2010Date of Patent: October 15, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Chien-Chang Su, Tsung-Hung Li, Da-Wen Lin, Wen-Sheh Huang
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Patent number: 8350586Abstract: Provided is a method of de-embedding. The method includes forming a test structure having a device-under-test embedded therein, the test structure having left and right pads coupling the device-under-test, the device-under-test dividing the test structure into left and right half structures, the left and right half structures each having intrinsic transmission parameters; forming a plurality of dummy test structures, each dummy test structure including a left pad and a right pad; measuring transmission parameters of the test structure and the dummy test structures; and deriving intrinsic transmission parameters of the device-under-test using the intrinsic transmission parameters of the left and right half structures and the transmission parameters of the test structure and the dummy test structures.Type: GrantFiled: July 2, 2009Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ying Cho, Jiun-Kai Huang, Wen-Sheh Huang, Sally Liu
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Publication number: 20120267626Abstract: A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Ying Cho, Jiun-Kai Huang, Wen-Sheh Huang, Chin-Wei Kuo, Min-Chie Jeng
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Patent number: 8187928Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. A plasma doping (PLAD) process is performed to at least a portion of the substrate that is adjacent to the gate structure. The doped portion of the substrate is annealed in an ambient with an oxygen-containing chemical.Type: GrantFiled: September 21, 2010Date of Patent: May 29, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: De-Wei Yu, Chun Hsiung Tsai, Yu-Lien Huang, Chien-Tai Chan, Wen-Sheh Huang