Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: A method and system for inspecting deviation in dynamic characteristics of a feeding system are provided, and the method includes: exciting the feeding system and detecting vibrations of a subcomponent of a component to be inspected of the feeding system to generate a monitoring excitation signal in a monitoring mode; calculating, by a modal analysis method, monitoring eigenvalues and monitoring eigenvectors of the monitoring excitation signal; determining, by a modal verification method, similarity between the monitoring eigenvalues and standard eigenvalues of a digital twin model and similarity between the monitoring eigenvectors and standard eigenvectors of the digital twin model; determining that the dynamic characteristics of the subcomponent are deviated, when the monitoring eigenvalues and monitoring eigenvectors are not similar to the standard eigenvalues and standard eigenvectors. Therefore, the subcomponent whose dynamic characteristics are deviated can be sensed remotely and precisely.

Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.

Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: A range Doppler angle detection method executed by a range Doppler angle detection device includes steps of: receiving a first sensing signal and a second sensing signal; performing 1D Fast Fourier Transform (FFT) and 2D FFT to the first sensing signal for calculating one first 2D FFT map; performing the 1D FFT and the 2D FFT to the second sensing signal for calculating one second 2D FFT map; picking up one column of the first 2D FFT map and one column of the second 2D FFT map according to a given Doppler index; performing the 3D FFT to the picked column of the first 2D FFT map and the picked column of the second 2D FFT map for calculating a range Doppler angle. Therefore, a computation loading of the gesture recognition function can be reduced.

Abstract: A range Doppler angle detection method executed by a range Doppler angle detection device includes steps of: receiving a first sensing signal and a second sensing signal; performing 1D Fast Fourier Transform (FFT) and 2D FFT to the first sensing signal for calculating one first 2D FFT map; performing the 1D FFT and the 2D FFT to the second sensing signal for calculating one second 2D FFT map; picking up one column of the first 2D FFT map and one column of the second 2D FFT map according to a given Doppler index; performing the 3D FFT to the picked column of the first 2D FFT map and the picked column of the second 2D FFT map for calculating a range Doppler angle. Therefore, a computation loading of the gesture recognition function can be reduced.

Abstract: The invention discloses an oscillator, including a voltage switching circuit, a voltage adjustment circuit and a frequency generation circuit. The voltage switching circuit receives an output voltage signal whereby the output voltage signal switches a first input voltage signal to a first voltage level signal and switches a second input voltage signal to a second voltage level signal. The voltage adjustment circuit receives the first voltage level signal and the second voltage level signal, whereby the first voltage level signal and the second voltage level signal generate the first adjustment voltage signal and the second adjustment voltage signal. The frequency generation circuit is connected to the voltage adjustment circuit, and receives the first adjustment voltage signal and the second adjustment voltage signal to generate the first output frequency signal and the second output frequency signal according to the first adjustment voltage signal and the second adjustment voltage signal.

Abstract: A system for reducing a mismatch between an in-phase (I) signal and a quadrature phase (Q) signal is disclosed. The system includes a phase compensation block comprising an infinite impulse response (IIR) filter configured to reduce a first portion of a mismatch between an I signal and a Q signal, wherein the first portion includes frequency selective phase mismatch. The system further includes a gain compensation block comprising a finite impulse response (FIR) filter configured to reduce a second portion of the mismatch, wherein the second portion includes frequency selective gain mismatch. The phase compensation block and the gain compensation block are calibrated at least in part based on a loopback signal, wherein the loopback signal is routed from a transmitting portion of a radio frequency (RF) circuitry back to a receiving portion of the RF circuitry.

Abstract: A system for reducing a mismatch between an in-phase (I) signal and a quadrature phase (Q) signal is disclosed. The system includes a phase compensation block comprising an infinite impulse response (IIR) filter configured to reduce a first portion of a mismatch between an I signal and a Q signal, wherein the first portion includes frequency selective phase mismatch. The system further includes a gain compensation block comprising a finite impulse response (FIR) filter configured to reduce a second portion of the mismatch, wherein the second portion includes frequency selective gain mismatch. The phase compensation block and the gain compensation block are calibrated at least in part based on a loopback signal, wherein the loopback signal is routed from a transmitting portion of a radio frequency (RF) circuitry back to a receiving portion of the RF circuitry.