Abstract: A display driver circuit for high resolution and high frame rate and a display device using the same are provided. A display driver circuit for high resolution and high frame rate includes a GAMMA output circuit, multiple digital-to-analog converters (DACs), multiple source operation amplifiers and at least a pre-charging circuit. The GAMMA output circuit outputs multiple grayscales of GAMMA voltages. Each DAC receives the GAMMA voltages and provides an output data voltage according to display data. Input terminals of the source operation amplifiers correspondingly coupled to output terminals of the DACs receive the corresponding output data voltages. The pre-charging circuit coupled between the input terminal of at least one of the source operation amplifiers and the output terminal of at least one of the DACs pre-charges the input terminal of the coupled source operation amplifier, so that an output terminal of the coupled source operation amplifier has fast response to the received output data voltage.

Abstract: A display device includes a timing control circuit and a data driving circuit. The data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The data driving circuit also receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from a frequency of the second clock signal.

Abstract: A display device includes a timing control circuit, a first data driving circuit, and a second data driving circuit. The first data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The second data driving circuit receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from that of the second clock signal.

Abstract: A semiconductor device includes a p-substrate, a digital circuit unit, and an analogy circuit unit. The digital circuit unit includes a deep n-well, a first p-type semiconductor element, a first n-type semiconductor element, and a p-well. The deep n-well is formed on the p-substrate, the first p-type semiconductor element and the p-well are formed on the deep n-well, and the first n-type semiconductor element formed on the p-well. The analogy circuit unit includes a second p-type semiconductor element, a second n-type semiconductor element, and an n-well. The second n-type semiconductor element and the n-well are formed on the p-substrate, and the second p-type semiconductor element formed on the n-well.

Abstract: A display device includes a timing control circuit and a data driving circuit. The data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The data driving circuit also receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from a frequency of the second clock signal.

Abstract: A display device includes a timing control circuit, a first data driving circuit, and a second data driving circuit. The first data driving circuit receives the first clock embedded training data from the timing control circuit, performs a first clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a first clock signal, and receives the first clock embedded image data from the timing control circuit. The second data driving circuit receives a second clock embedded training data from the timing control circuit, performs a second clock training to adjust a work frequency of the data driving circuit to be equal to the frequency of a second clock signal, and receives the second clock embedded image data from the timing control circuit. The frequency of the first clock signal is different from that of the second clock signal.

Abstract: A source driver for an LCD panel includes two gm stages and two output buffers. In a normal operation mode, the first gm stage and the first output buffer establish a unity gain buffer to amplify a positive polarity analog voltage to be a positive polarity output voltage, and the second gm stage and the second output buffer establish a unity gain buffer to amplify a negative polarity analog voltage to be a negative polarity output voltage. In a polarity inversion mode, the second gm stage and the first output buffer establish a unity gain buffer to amplify a positive polarity analog voltage to be a positive polarity output voltage, and the first gm stage and the second output buffer establish a unity gain buffer to amplify a negative polarity analog voltage to be a negative polarity output voltage.

Abstract: A voltage interpolation buffer for interpolating voltages by adjusting ratio of bias currents includes a first difference voltage to current unit for outputting corresponding difference current according to a first voltage, a first bias current and voltage of a voltage output end, a second difference voltage to current unit for outputting corresponding difference current according to a second voltage, a second bias current and the voltage of the voltage output end, and a current to voltage unit coupled to the first difference voltage to current unit, the second difference voltage to current unit and the voltage output end for outputting a interpolation result of the first voltage and the second voltage corresponding to a ratio of the first bias current and the second bias current according to the difference currents outputted by the first difference voltage to current unit and the second difference voltage to current unit.

Abstract: A voltage interpolation buffer for interpolating voltages by adjusting ratio of bias currents includes a first difference voltage to current unit for outputting corresponding difference current according to a first voltage, a first bias current and voltage of a voltage output end, a second difference voltage to current unit for outputting corresponding difference current according to a second voltage, a second bias current and the voltage of the voltage output end, and a current to voltage unit coupled to the first difference voltage to current unit, the second difference voltage to current unit and the voltage output end for outputting a interpolation result of the first voltage and the second voltage corresponding to a ratio of the first bias current and the second bias current according to the difference currents outputted by the first difference voltage to current unit and the second difference voltage to current unit.

Abstract: A method for driving an LCD panel having a plurality of pixels corresponding to a matrix includes receiving an image data, setting polarities of the plurality of pixels according to an LCD panel driving procedure, dividing the plurality of pixels into a plurality of groups by lines of the matrix according to polarities of pixels corresponding to a column of the matrix, and sequentially scanning the pixels of the groups, so as to show the image data.

Abstract: A power-saving device for a driving circuit of a liquid crystal display panel is provided. The device comprises a first switch, a first capacitor, a second switch, a second capacitor, a third switch, an output buffer and a common electrode or a data line. The first capacitor and the second capacitor are coupled to the common electrode or the data line through the first switch and the second switch respectively. The output buffer is coupled to the common electrode or the data line through the third switch. The output buffer charges or discharges a ground-referenced equivalent capacitor of the data line or the common electrode. The device uses the switches to conduct positive and negative electric charges to the capacitors so that charges produced during the charging and discharging in the driving circuits of the common electrodes and data line can be stored and recycled to avoid unnecessary power waste.