Patents by Inventor Wen Siang LEW
Wen Siang LEW has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11751483Abstract: According to various embodiments, a spin diode device may include a magnetic tunnel junction stack. The magnetic tunnel junction stack may include a lower magnetic layer, a tunnel barrier layer over the lower magnetic layer, and an upper magnetic layer over the tunnel barrier layer. The lower magnetic layer may include a lower magnetic film. The tunnel barrier layer comprising an insulating material. The upper magnetic layer may include an upper magnetic film. Each of the lower magnetic film and the upper magnetic film may have perpendicular magnetic anisotropy.Type: GrantFiled: December 28, 2020Date of Patent: September 5, 2023Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Wai Cheung Law, Grayson Dao Hwee Wong, Kazutaka Yamane, Chim Seng Seet, Wen Siang Lew
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Publication number: 20220385292Abstract: A magnetic logic device having two magnetic elements and a conductive element coupled to the two magnetic elements and arranged at least substantially perpendicular to the magnetic elements, wherein the device is configured, for each magnetic element, to have a magnetisation state with a perpendicular easy axis, and to switch the magnetisation state in response to a spin current generated in the magnetic element in response to a write current applied to the magnetic element, and configured to generate, as an output, a Hall voltage across the conductive element in response to a respective read current applied to each magnetic element, wherein a magnitude of the Hall voltage is variable, depending on a direction of the magnetisation state of each magnetic element and a direction of the respective read current applied to each magnetic element, for the device to provide outputs corresponding to one of a plurality of logical operations.Type: ApplicationFiled: November 2, 2020Publication date: December 1, 2022Applicant: Nanyang Technological UniversityInventors: Chu Keong Gerard Joseph LIM, Chandrasekhar MURAPAKA, Wen Siang LEW
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Publication number: 20220209102Abstract: According to various embodiments, a spin diode device may include a magnetic tunnel junction stack. The magnetic tunnel junction stack may include a lower magnetic layer, a tunnel barrier layer over the lower magnetic layer, and an upper magnetic layer over the tunnel barrier layer. The lower magnetic layer may include a lower magnetic film. The tunnel barrier layer comprising an insulating material. The upper magnetic layer may include an upper magnetic film. Each of the lower magnetic film and the upper magnetic film may have perpendicular magnetic anisotropy.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: Wai Cheung LAW, Grayson Dao Hwee WONG, Kazutaka YAMANE, Chim Seng SEET, Wen Siang LEW
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Patent number: 10475495Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.Type: GrantFiled: February 14, 2018Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Chim Seng Seet, Kai Hung Alex See, Gerard Joseph Lim, Wen Siang Lew
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Patent number: 10468171Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.Type: GrantFiled: June 27, 2018Date of Patent: November 5, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Dimitri Houssameddine, Michael Nicolas Albert Tran, Chim Seng Seet, Kai Hung Alex See, Wen Siang Lew
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Publication number: 20190272874Abstract: According to embodiments of the present invention, a memory device is provided. The memory device includes an electrochemical metallization memory (ECM) cell and a valence change memory (VCM) cell arranged one over the other. According to further embodiments of the present invention, a method of forming a memory device, a method for controlling a memory device, and a memory array are also provided.Type: ApplicationFiled: September 12, 2017Publication date: September 5, 2019Inventors: Putu Andhita Dananjaya, Wen Siang Lew
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Publication number: 20190252600Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a first free layer that is magnetic, a second free layer that is magnetic, and an insertion layer positioned between the first and second free layers. The insertion layer is non-magnetic, and the insertion layer includes terbium.Type: ApplicationFiled: February 14, 2018Publication date: August 15, 2019Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Chim Seng Seet, Kai Hung Alex See, Gerard Joseph Lim, Wen Siang Lew
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Patent number: 10312442Abstract: Non-volatile memory (NVM) devices, resistive random access memory (RRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a non-volatile memory (NVM) device includes a first electrode and a second electrode positioned above the first electrode. Further, the NVM device includes a variable resistance material layer positioned between the first electrode and the second electrode. The variable resistance material layer contains magnesium oxide.Type: GrantFiled: September 21, 2017Date of Patent: June 4, 2019Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Danny Pak-Chum Shum, Desmond Jia Jun Loy, Wen Siang Lew
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Publication number: 20190088874Abstract: Non-volatile memory (NVM) devices, resistive random access memory (RRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a non-volatile memory (NVM) device includes a first electrode and a second electrode positioned above the first electrode. Further, the NVM device includes a variable resistance material layer positioned between the first electrode and the second electrode. The variable resistance material layer contains magnesium oxide.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Inventors: Danny Pak-Chum Shum, Desmond Jia Jun Loy, Wen Siang Lew
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Patent number: 10127016Abstract: A magnetic random number generator is disclosed. The magnetic random number generator comprises: a) a Hall cross structure comprising at least one magnetic nanowire with perpendicular magnetic anisotropy; b) an in-plane pulsed current generator operable to generate stochastic nucleation of domain walls (DWs) in the Hall cross structure; and c) a sensor configured to measure a parameter of the Hall cross structure upon DW nucleation, wherein said parameter has a value representing a random number. A greater number of Hall cross structures may be employed to generate a random number having a greater number of bits.Type: GrantFiled: January 20, 2017Date of Patent: November 13, 2018Assignee: NANYANG TECHNOLOGICAL UNIVERSITYInventors: Pankaj Sethi, Chandrasekhar Murapaka, Wen Siang Lew, Arindam Basu
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Publication number: 20170212728Abstract: A magnetic random number generator is disclosed. The magnetic random number generator comprises: a) a Hall cross structure comprising at least one magnetic nanowire with perpendicular magnetic anisotropy; b) an in-plane pulsed current generator operable to generate stochastic nucleation of domain walls (DWs) in the Hall cross structure; and c) a sensor configured to measure a parameter of the Hall cross structure upon DW nucleation, wherein said parameter has a value representing a random number. A greater number of Hall cross structures may be employed to generate a random number having a greater number of bits.Type: ApplicationFiled: January 20, 2017Publication date: July 27, 2017Inventors: Pankaj SETHI, Chandrasekhar MURAPAKA, Wen Siang LEW, Arindam BASU
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Patent number: 9502090Abstract: A memory device comprising a ferromagnetic data nanowire, a ferromagnetic driver nanowire, read element and/or a spaced write element positioned about the data nanowire, wherein driving a domain wall in the driver nanowire remotely drives a domain wall in the data nanowire past the read element and/or the write element.Type: GrantFiled: January 2, 2014Date of Patent: November 22, 2016Assignee: NANYANG TECHNOLOGICAL UNIVERSITYInventors: Wen Siang Lew, Indra Purnama, Chandra Sekhar Murapaka
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Patent number: 9431599Abstract: A non-volatile logic device, comprising: a first input element magnetizable along a first direction to impart or change a chirality of a domain wall traversing the first input element a second input element configured to transport the domain wall, a magnetization of the second input element along a second direction representing a second logical input; a bifurcated output section comprising a pair of output elements for receiving the domain wall from the second input element, a magnetization of at least part of the output elements being changeable by propagation of the domain wall along the output elements; and a non-magnetic conductive element; wherein the magnetization in an output element after propagation of the domain wall represents a value of a logical function selectable by passing an electrical current through the non-magnetic conductive element to induce a magnetic field of a desired magnitude and direction in the second input element.Type: GrantFiled: May 19, 2014Date of Patent: August 30, 2016Assignee: NANYANG TECHNOLOGICAL UNIVERSITYInventors: Wen Siang Lew, Chandrasekhar Murapaka, Indra Purnama, Sarjoosing Goolaup, Pankaj Sethi, Chinkhanlun Guite
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Publication number: 20160133827Abstract: A non-volatile logic device, comprising: a first input element magnetizable along a first direction to impart or change a chirality of a domain wall traversing the first input element a second input element configured to transport the domain wall, a magnetization of the second input element along a second direction representing a second logical input; a bifurcated output section comprising a pair of output elements for receiving the domain wall from the second input element, a magnetization of at least part of the output elements being changeable by propagation of the domain wall along the output elements; and a non-magnetic conductive element; wherein the magnetization in an output element after propagation of the domain wall represents a value of a logical function selectable by passing an electrical current through the non-magnetic conductive element to induce a magnetic field of a desired magnitude and direction in the second input element.Type: ApplicationFiled: May 19, 2013Publication date: May 12, 2016Inventors: Wen Siang LEW, Chandra Sekhar MURAPAKA, Indra PURNAMA, Sarjoosing GOOLAUP, Pankaj SETHI, Chinkhanlun GUITE
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Publication number: 20160064060Abstract: A method of forming a domain wall in a nanowire, the method comprising the steps of: a) providing a conductive strip orthogonally to a nanowire adjacent a free end of the nanowire, the nanowire having an original magnetization direction; b) pulsing a current through the conductive strip to generate an Oersted field having a direction opposite to the original magnetization direction such that magnetization direction of a portion of the nanowire transversed by the conductive strip becomes opposite to the original magnetization direction, the domain wall being generated in the nanowire at a location defined between the portion of the nanowire transversed by the conductive strip and a second end of the nanowire, wherein no external magnetic field is provided during formation of the domain wall.Type: ApplicationFiled: September 2, 2015Publication date: March 3, 2016Inventors: Chinkhanlun GUITE, Inn Seng KERK, Chandra Sekhar MURAPAKA, Wen Siang LEW
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Publication number: 20150371696Abstract: A memory device comprising a ferromagnetic data nanowire, a ferromagnetic driver nanowire, read element and/or a spaced write element positioned about the data nanowire, wherein driving a domain wall in the driver nanowire remotely drives a domain wall in the data nanowire past the read element and/or the write element.Type: ApplicationFiled: January 2, 2014Publication date: December 24, 2015Inventors: Wen Siang LEW, Indra PURNAMA, Chandra Sekhar MURAPAKA