Abstract: Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

Abstract: Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

Abstract: Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

Abstract: A new technique using arrival locked loop technology to produce a spread spectrum clock signal with random frequency modulation and with precise variable frequency spread is presented. The arrival locked loop includes three modules, the arrival comparator with a precise spread control, the loop filter and the VCO. An arrival locked loop is made unstable and oscillates at a certain frequency to produce a low frequency modulation signal on the final error correction output to spread the high frequency output signal from VCO in frequency. The period of frequency spread in each cycle of the low frequency modulation signal also increases by a small random amount of time cycle after cycle until the period of frequency spread becomes so long that cycle-slip is produced to the punctual signal at the input of arrival comparator to reset the period of frequency spread to a small amount.

Abstract: A system and method for detecting a phase and a frequency and an arrival-time difference between two signals (118 and 120) that minimizes delay and jitter, and has stable operation even when the two signals (118 and 120) are essentially identical. The system includes two single-ended charge-pump (188), phase-frequency detection (PFD) circuits (280). The first PFD is stable when a reference signal, supplied to a polarity determining flip-flop, leads the signal to be synchronized. A second, complementary, PFD circuit is stable, but has an inverted polarity output, when the signal to be synchronized, supplied to a polarity determining flip-flop, leads the reference signal. A polarity-selection logic-circuit (284) ensures that the first activated PFD controls the polarity a single-ended charge pump (188) for a time-period determined by the delay between the activation of the polarity determining and non-polarity determining flip-flops of the selected PFD.

Abstract: This patent disclosure presents circuits, systems and methods to produce a stable signal from a reference signal source. These new inventions are far better than the current technologies to provide a stable signal with less phase noises. This new invention also provides a new approach to analyze the feedback control loop without using the traditional feedback control theory.

Abstract: This patent disclosure presents circuits, systems and methods to spread a clock signal to produce a random spreading for the clock signal that offers the maximum possible power density reduction for the spurious radiations generated from the clock signal and its harmonics. These new inventions utilize a non-linear feedback control loop to assist in generation of the spread spectrum clock and result in electronic products that can pass the FCC requirements for spurious radiations generated by the clock signal and its harmonics without utilizing expensive shielding and other EMI suppression methods.

Abstract: This patent disclosure presents circuits, systems and methods to extract the clock signal from a data stream. This new invention is far better than the current technologies in the range of frequency locking and tracking. Since the new data clock recovery system is built by digital circuits only, it can be implemented inside an IC easily. This invention is especially helpful for high speed data communication products since the clock can be recovered at full data rate.

Abstract: Positive logic circuits, systems and methods using MOSFETs operated in a depletion-mode, including electrostatic discharge protection circuits (ESD), non-inverting latches and buffers, and one-to-three transistor static random access memory cells. These novel circuits supplement enhancement-mode MOSFET technology and are also intended to improve the reliability of the complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) products.

Abstract: A system and method for detecting a phase and a frequency and an arrival-time difference between two signals (118 and 120) that minimizes delay and jitter, and has stable operation even when the two signals (118 and 120) are essentially identical. The system includes two single-ended charge-pump (188), phase-frequency detection (PFD) circuits (280). The first PFD is stable when a reference signal, supplied to a polarity determining flip-flop, leads the signal to be synchronized. A second, complementary, PFD circuit is stable, but has an inverted polarity output, when the signal to be synchronized, supplied to a polarity determining flip-flop, leads the reference signal. A polarity-selection logic-circuit (284) ensures that the first activated PFD controls the polarity a single-ended charge pump (188) for a time-period determined by the delay between the activation of the polarity determining and non-polarity determining flip-flops of the selected PFD.

Abstract: A d.c.-coupled video clamping circuit is disclosed for operation with normal video signals and sync suppressed scrambled video signals. For receiving normal video signals, a feedback path detects variations in sync tip level from a reference level and applies a corresponding control voltage to a d.c. signal amplifier, thereby to clamp and maintain the sync tip at a fixed (black) level. For receiving sync suppressed scrambled video signals, the feedback path is disabled and a fixed reference voltage is applied to the d.c. signal amplifier.