Patents by Inventor Wen-Ta Tsai

Wen-Ta Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6608388
    Abstract: A delamination-preventing substrate and a semiconductor package with the substrate are provided. A metal layer and a solder mask layer are sequentially laminated on a chip attach area of a substrate, and both formed with corresponding openings for partly exposing the substrate. This allows an adhesive for chip-bonding use to be directly attached to the substrate via the openings, so as to reduce contact area between the adhesive and the metal layer, and to increase bonding between the substrate and a chip mounted on the substrate by means of the adhesive. Direct contact between the adhesive and the substrate also helps reduce stress generated between the chip and substrate, thereby preventing stress-induced delamination. Due to weak adhesion between adhesive and metal materials, reduced contact area between the adhesive and the metal layer would further enhance bonding of the chip to the substrate, thereby assuring quality of fabricated package products.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: August 19, 2003
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yuan-Fu Lin, Wen-Ta Tsai
  • Patent number: 6590279
    Abstract: A dual-chip integrated circuit package and a method for manufacturing such a dual-chip integrated circuit package are proposed, which can help prevent the occurrence of cracking and delamination in the chips and the occurrence of voids in the encapsulant during the manufacture process. The dual-chip integrated circuit package is constructed on a leadframe having a plurality of first leads and a plurality of second leads and at least a pair of support members between the first and second leads. Further, the dual-chip integrated circuit package includes at least one support member attached to the front side of the first integrated circuit chip for providing a support to the bonding pads on the second integrated circuit chip; the support member being not smaller in dimension than the area where the bonding pads on the second integrated circuit chip are located.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: July 8, 2003
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Ping Huang, Lian-Cherng Chiang, Wen-Ta Tsai
  • Publication number: 20030080439
    Abstract: A delamination-preventing substrate and a semiconductor package with the substrate are provided. A metal layer and a solder mask layer are sequentially laminated on a chip attach area of a substrate, and both formed with corresponding openings for partly exposing the substrate. This allows an adhesive for chip-bonding use to be directly attached to the substrate via the openings, so as to reduce contact area between the adhesive and the metal layer, and to increase bonding between the substrate and a chip mounted on the substrate by means of the adhesive. Direct contact between the adhesive and the substrate also helps reduce stress generated between the chip and substrate, thereby preventing stress-induced delamination. Due to weak adhesion between adhesive and metal materials, reduced contact area between the adhesive and the metal layer would further enhance bonding of the chip to the substrate, thereby assuring quality of fabricated package products.
    Type: Application
    Filed: June 19, 2002
    Publication date: May 1, 2003
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Yuan-Fu Lin, Wen-Ta Tsai
  • Patent number: 6428849
    Abstract: The invention discloses a method for producing a nitrogen-silicon containing stainless steel layer on a metal. The method includes a pack cementation process involving the use of silicon nitride, silica and sodium fluoride as the source materials.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: August 6, 2002
    Assignee: National Science Council
    Inventors: Wen-Ta Tsai, Hung-Wen Hsu
  • Patent number: 6307257
    Abstract: A dual-chip integrated circuit (IC) package is provided, which is characterized in the use of a an extending portion formed from the leads of a leadframe to provide firm support to the bonding pads on the chips. The dual-chip integrated circuit package utilizes a leadframe having a first leads and a second leads, with a spacing being defined between the first and second leads; and the first leads is extended toward the spacing to form the extending portion at a downset position with respect to the second plane where the leadframe positions leads. A first integrated circuit chip is mounted on the extending portion in such a manner that the front side thereof is attached to the extending portion; and a second integrated circuit chip is attached to the first integrated circuit chip in a back-to-back manner. The bonding pads on the two integrated circuit chips are electrically connected to the first and second leads via a plurality of bonding wires.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: October 23, 2001
    Assignee: Siliconware Precision Industries, Co., Ltd.
    Inventors: Chien-Ping Huang, Lian-Cherng Chiang, Wen-Ta Tsai
  • Patent number: 6264535
    Abstract: A wafer sawing/grinding process capable of removing cracks and chipping resulted from a wafer sawing operation. A silicon wafer having an active surface and a back surface is provided. A first tape is attached to the back surface of the wafer and then the wafer is sawn along kerfs between neighboring silicon chips. A second tape is attached to the active surface of the silicon wafer before removing the first tape. The back surface of the wafer is then ground until the wafer reaches a desired thickness. A third tape is attached to the ground back surface of the wafer before removing the second tape.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: July 24, 2001
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shi-Yu Chang, Chin-Te Chen, Wen-Ta Tsai
  • Patent number: 5496593
    Abstract: A process for producing a nitrogen-alloyed stainless steel layer on steel by applying nitride containing mixed metal powder or stainless powder to the steel surface, and thereafter treating the steel with laser beams.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: March 5, 1996
    Assignee: National Science Council
    Inventors: Wen-Ta Tsai, Chong-Cheng Huang, Ju-Tung Lee
  • Patent number: 5411770
    Abstract: The surface of stainless steel can be hardened by coating a silicon nitride gel and then scanning by CO.sub.2 laser to form a surface alloy layer thereon. The thickness and hardness of the surface alloy layer are both uniform. The Vicker's hardness of the layer can be as high as 1200 Hv. This method can be operated in a common atmosphere or nitride atmosphere at normal pressure, therefore it is more economic than ion nitriding or plasma nitriding.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: May 2, 1995
    Assignee: National Science Council
    Inventors: Wen-Ta Tsai, Ju-Tung Lee, Tai-Hwang Lai
  • Patent number: D468140
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: January 7, 2003
    Inventor: Wen-Ta Tsai
  • Patent number: D470322
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: February 18, 2003
    Inventor: Wen-Ta Tsai
  • Patent number: D475210
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: June 3, 2003
    Assignee: Zhejiang Himax Furniture Industry Corp. Ltd.
    Inventor: Wen-Ta Tsai
  • Patent number: D476495
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: July 1, 2003
    Inventor: Wen-Ta Tsai