Patents by Inventor Wen-Tai Lu
Wen-Tai Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10269568Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.Type: GrantFiled: January 2, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wen-Tai Lu
-
Patent number: 10103025Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.Type: GrantFiled: November 28, 2016Date of Patent: October 16, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wen-Tai Lu
-
Publication number: 20180145074Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.Type: ApplicationFiled: January 2, 2018Publication date: May 24, 2018Inventor: Wen-Tai Lu
-
Patent number: 9653581Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.Type: GrantFiled: January 26, 2016Date of Patent: May 16, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Wen-Tai Lu, Chun-Feng Nieh, Hou-Yu Chen, Yu-Chang Lin
-
Publication number: 20170077095Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Inventor: Wen-Tai Lu
-
Patent number: 9508714Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.Type: GrantFiled: October 28, 2014Date of Patent: November 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wen-Tai Lu
-
Publication number: 20160141394Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.Type: ApplicationFiled: January 26, 2016Publication date: May 19, 2016Inventors: Wen-Tai Lu, Chun-Feng Nieh, Hou-Yu Chen, Yu-Chang Lin
-
Patent number: 9252271Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.Type: GrantFiled: November 27, 2013Date of Patent: February 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wen-Tai Lu, Hou-Yu Chen, Yu-Chang Lin, Chun-Feng Nieh
-
Patent number: 9166044Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: GrantFiled: September 27, 2013Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Tai Lu, Hou-Yu Chen, Shyh-Horng Yang
-
Patent number: 9123564Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first semiconductor device. The first semiconductor device includes a first active region having a first doped region and a second doped region over the first doped region. The second doped region includes a first bottom portion and a first sidewall. The first bottom portion includes a first bottom portion inner surface, a first bottom portion outer surface, a first bottom portion height and a first bottom portion width. The first sidewall includes a first sidewall inner surface, a first sidewall outer surface, a first sidewall width and a first sidewall height, the first sidewall height greater than the first bottom portion height. A method of making a semiconductor device is also provided.Type: GrantFiled: December 5, 2013Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Chang Lin, Wen-Tai Lu, Li-Ting Wang, Chun-Feng Nieh, Hou-Yu Chen, Huicheng Chang
-
Publication number: 20150162330Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first semiconductor device. The first semiconductor device includes a first active region having a first doped region and a second doped region over the first doped region. The second doped region includes a first bottom portion and a first sidewall. The first bottom portion includes a first bottom portion inner surface, a first bottom portion outer surface, a first bottom portion height and a first bottom portion width. The first sidewall includes a first sidewall inner surface, a first sidewall outer surface, a first sidewall width and a first sidewall height, the first sidewall height greater than the first bottom portion height. A method of making a semiconductor device is also provided.Type: ApplicationFiled: December 5, 2013Publication date: June 11, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yu-Chang Lin, Wen-Tai Lu, Li-Ting Wang, Chun-Feng Nieh, Hou-Yu Chen, Huicheng Chang
-
Publication number: 20150145066Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wen-Tai Lu, Hou-Yu Chen, Yu-Chang Lin, Chun-Feng Nieh
-
Publication number: 20150091086Abstract: Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin, masking dielectric layer portions, and a raised epitaxial lightly doped source/drain (LDD) region. The substrate includes the fin. The masking dielectric layer portions are along sidewalls of the fin. An upper portion of the fin protrudes from the masking dielectric layer portions. A first spacer is along a sidewall of a gate structure over a channel region of the fin. A second spacer is along the first spacer. The raised epitaxial LDD region is on the upper portion of the fin, and the raised epitaxial LDD region adjoins a sidewall of the first spacer and is disposed under the second spacer. The raised epitaxial LDD region extends from the upper portion of the fin in at least two laterally opposed directions and a vertical direction.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Tai Lu, Hou-Yu Chen, Shyh-Horng Yang
-
Publication number: 20150041923Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventor: Wen-Tai Lu
-
Patent number: 8883570Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.Type: GrantFiled: July 3, 2012Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Wen-Tai Lu
-
Publication number: 20140008734Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.Type: ApplicationFiled: July 3, 2012Publication date: January 9, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Wen-Tai Lu
-
Patent number: 6894352Abstract: A method for fabricating a single-electron transistor (SET). A one dimensional channel is formed between source and drain on a silicon-on-insulator substrate, and the separated polysilicon sidewall spacer gates are formed by electron-beam lithographically etching process in a self-aligned manner. Operation of the single-electron transistor with self-aligned polysilicon sidewall spacer gates is achieved by applying external bias to the self-aligned polysilicon sidewall spacer gates to form two potential barriers and a quantum dot capable of storage charges between the two potential barriers. A metal upper gate is finally formed and biased to induce a two-dimensional electron gas (2DEG) and control the energy level of the quantum well.Type: GrantFiled: June 25, 2003Date of Patent: May 17, 2005Inventors: Shu-Fen Hu, Yung-Chun Wu, Wen-Tai Lu, Shiue-Shin Liu, Tiao-Yuan Huang, Tien-Sheng Chao
-
Publication number: 20040061173Abstract: A method for fabricating a single-electron transistor (SET). A one dimensional channel is formed between source and drain on a silicon-on-insulator substrate, and the separated polysilicon sidewall spacer gates are formed by electron-beam lithographically etching process in a self-aligned manner. Operation of the single-electron transistor with self-aligned polysilicon sidewall spacer gates is achieved by applying external bias to the self-aligned polysilicon sidewall spacer gates to form two potential barriers and a quantum dot capable of storage charges between the two potential barriers. A metal upper gate is finally formed and biased to induce a two-dimensional electron gas (2DEG) and control the energy level of the quantum well.Type: ApplicationFiled: June 25, 2003Publication date: April 1, 2004Inventors: Shu-Fen Hu, Yung-Chun Wu, Wen-Tai Lu, Shiue-Shin Liu, Tiao-Yuan Huang, Tien-Sheng Chao