Patents by Inventor Wen-To HUANG

Wen-To HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387454
    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 12148735
    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20240379401
    Abstract: Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Chung-Pin CHOU, Kai-Lin CHUANG, Sheng-Wen HUANG, Yan-Cheng CHEN, Jun Xiu LIU
  • Patent number: 12141187
    Abstract: A file managing method for a digital apparatus includes (a) establishing a folder corresponding to a file type generated in an operational mode of the digital apparatus, and (b) storing a file according to its file type to the folder corresponding to the file type established in step (a).
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: November 12, 2024
    Assignee: Intellectual Ventures I LLC
    Inventor: Chih-Wen Huang
  • Patent number: 12143580
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing a video picture partitioned into blocks with one or more partition constraints. The video encoding or decoding system receives input data of a current block and checks whether a predefined splitting type is allowed to partition the current block according to first and second constraints. The first constraint restricts each sub-block partitioned from the current block to be completely contained in one pipeline unit, and the second constraint restricts each sub-block partitioned from the current block to contain one or more complete pipeline units. The pipeline units are non-overlapping units in the video picture designed for pipeline processing. The current block is not partitioned by the predefined splitting type if any sub-block partitioned by the predefined splitting type violates both the first and second constraints. The system encodes or decodes the current block.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: November 12, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 12137080
    Abstract: A method and system for mitigating a threat associated with network data packets are provided. The method commences with receiving, by an authentication server, a request for access to a server from a client. The method further includes authenticating the client by the authentication server. The authentication includes providing an authentication token to the client. The method continues with receiving, by a mitigation device, from the client, at least one network packet directed to the server. The at least one network packet embeds the authentication token. The method further includes validating, by the mitigation device, authenticity of the authentication token and selectively forwarding, based on the validation, the at least one network packet to the server. The authentication token is independently generated by the authentication server, the mitigation device, and the server using a shared token generation algorithm based on a hash salt value.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: November 5, 2024
    Inventors: Yutun (Tony) Tseng, Ahmed Abdelhalim, Vernon Richard Groves, Ching-Wen Huang
  • Publication number: 20240365493
    Abstract: A lifting module for a chassis and an electronic device including the lifting module are provided. The lifting module includes a sidewall bracket, a lifting bracket, a sliding button assembly, and a driven assembly. The sidewall bracket is disposed on a side frame of the chassis. The lifting bracket is movably connected to the sidewall bracket. The sliding button assembly is slidably disposed on the side frame of the chassis. Part of the sliding button assembly is exposed from the chassis. The driven assembly is movably disposed on the sidewall bracket. The driven assembly is connected to interact the sliding button assembly and the lifting bracket. The lifting bracket is driven to move relative to the sidewall bracket selectively by the sliding button assembly through the driven assembly.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 31, 2024
    Applicant: Wistron Corporation
    Inventors: Yin Tseng Lu, Chih Wei Kuo, YUCHUN HUNG, Tsung Han Yu, Hsiang Wen Huang, Chen Wei Tsai
  • Publication number: 20240363707
    Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
  • Publication number: 20240363672
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first substrate comprising a first semiconductor material. A first light sensor is disposed within the first substrate. The first light sensor is configured to absorb electromagnetic radiation within a first wavelength range. A second light sensor is disposed within an absorption structure underlying the first substrate. The second light sensor is configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range. The absorption structure underlies the first light sensor and comprises a second semiconductor material different from the first semiconductor material.
    Type: Application
    Filed: August 2, 2023
    Publication date: October 31, 2024
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Sung-Wen Huang Chen
  • Patent number: 12130359
    Abstract: Systems, devices, and methods for ultrasonic imaging by sparse sampling are provided. In one embodiment, an ultrasound imaging system comprises an array of ultrasound transducer elements, electronic circuitry in communication with the array of ultrasound transducer elements and configured to select a first receive aperture of the array comprising a plurality of contiguous ultrasound transducer elements and at least one non-contiguous ultrasound transducer element, and a beamformer in communication with the electronic circuitry. Each ultrasound transducer element of the first receive aperture is configured to receive reflected ultrasound echoes and generate an electrical signal representative of imaging data.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 29, 2024
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Sheng-Wen Huang, Changhong Hu, Douglas Robert Maxwell, David Hope Simpson, James Robertson Jago, Francois Guy Gerard Marie Vignon, Jun Seob Shin, Xiaowen Hu, Unmin Bae
  • Publication number: 20240357153
    Abstract: Method and apparatus for template matching with a determined area are disclosed. According to this method, a current template comprising current neighbouring pixels on an above side of the current block, on a left side of the current block, or a combination thereof for a current block is received. An area in a reference picture is then determined, where the reference picture corresponds to a previously coded picture. A matching result between a restricted reference template of a reference block and the current template is then determined, wherein the restricted reference template is generating by using only neighbouring reference pixels of a reference template inside the determined area, the reference template has a same shape as the current template, and a location of the reference template is determined according to a target motion vector (MV) from the current template.
    Type: Application
    Filed: August 18, 2022
    Publication date: October 24, 2024
    Inventors: Chun-Chia CHEN, Olena CHUBACH, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20240357082
    Abstract: A video coding system that uses template matching (TM) to improve signaling of coding modes is provided. The system receives data to be encoded or decoded as a current block of a current picture of a video. The system identifies a set of pixels neighboring the current block as a current template. The system identifies a reference template of each candidate coding mode in a plurality of candidate coding modes. The system computes a template matching (TM) cost for each candidate coding mode based on matching the current template with the reference template of the candidate coding mode. The system selects a candidate coding mode from the plurality of candidate coding modes based on the computed TM costs. The system reconstructs the current block or encoding the current block into a bitstream by using selected candidate coding mode.
    Type: Application
    Filed: August 18, 2022
    Publication date: October 24, 2024
    Inventors: Olena CHUBACH, Chun-Chia CHEN, Man-Shu CHIANG, Tzu-Der CHUANG, Ching-Yeh CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20240357081
    Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, input data associated with a current block of a video unit in a current picture are received. Motion compensation is then applied to the current block according to an initial motion vector (MV) to obtain initial motion-compensated predictors of the current. After applying the motion compensation to the current block, template-matching MV refinement is applied to the current block to obtain a refined MV for the current block. The current block is then encoded or decoded using information including the refined MV. The method may further comprise determining gradient values of the initial motion-compensated predictors. The initial motion-compensated predictors can be adjusted by taking into consideration of the gradient values and/or MV difference between the refined and initial MVs.
    Type: Application
    Filed: August 18, 2022
    Publication date: October 24, 2024
    Inventors: Chun-Chia CHEN, Olena CHUBACH, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20240357083
    Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, a current template for a current block is determined, where the current template includes an inside current template including inside prediction samples or inside partially reconstructed samples inside the current block. The inside partially reconstructed samples are derived by adding a DC value of the current block to the inside prediction samples. Corresponding candidate reference templates associated with the current block are determined at a set of candidate locations. A location of a target reference template among the candidate reference templates that achieves a best match between the current template and the candidate reference templates is determined. An initial motion vector (MV) is then refined according to the location of the target reference template.
    Type: Application
    Filed: August 12, 2022
    Publication date: October 24, 2024
    Inventors: Olena CHUBACH, Chun-Chia CHEN, Man-Shu CHIANG, Tzu-Der CHUANG, Ching-Yeh CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20240357084
    Abstract: A method and apparatus for video coding system that utilizes low-latency template-matching motion-vector refinement are disclosed. According to this method, a current template for the current block is determined, where at least one of current above template and current left template is removed or is located away from a respective above edge or a respective left edge of the current block and the current template is generated using reconstructed samples. Candidate reference templates, corresponding to the current template at respective candidate locations, associated with the current block at a set of candidate locations in a reference picture are determined. A location of a target reference template among the candidate reference templates is determined, where the target reference template achieves a best match with the current template. A refined motion vector (MV) is determined by refining an initial MV according to the location of the target reference template.
    Type: Application
    Filed: August 12, 2022
    Publication date: October 24, 2024
    Inventors: Olena CHUBACH, Chun-Chia CHEN, Man-Shu CHIANG, Tzu-Der CHUANG, Ching-Yeh CHEN, Chih-Wei HSU, Yu-Wen HUANG
  • Patent number: 12125270
    Abstract: A side by side image detection method and an electronic apparatus using the same are provided. The side by side image detection method includes the following steps. A first image with a first image size is obtained. A second image with a second image size that conforms to a side-by-side image format is detected within the first image by using a convolutional neural network model.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: October 22, 2024
    Assignee: Acer Incorporated
    Inventors: Sergio Cantero Clares, Chih-Haw Tan, Shih-Hao Lin, Chih-Wen Huang, Wen-Cheng Hsu, Chao-Kuang Yang
  • Publication number: 20240346741
    Abstract: In aspects of the disclosure, a method, a system, and a computer-readable medium, are provided. The method for processing graphics data with a graphics rendering pipeline comprising a mesh shader and a tiler, comprising outputting, by the mesh shader in response to an input of the graphics data, legacy mesh shader output parameters including vertices and primitives, and additional data with a meshlet bounding-box, or axis-aligned bounding box (AABB) structure; sending the AABB to the tiler as an input, and generating, by the tiler, a visibility stream according to the AABB, wherein each entity of the visibility stream indicates that the AABB is fully visible, partially visible, or invisible in the view frustum; and sending the visibility stream back to the tiler as a further input along with the legacy mesh shader output parameters for coming rasterization in a fragment pass.
    Type: Application
    Filed: April 4, 2024
    Publication date: October 17, 2024
    Inventors: Chengping Luo, You-Ming Tsao, Bozhan Chen, Sheng-Wen Huang
  • Publication number: 20240345211
    Abstract: An electronic device and a control method thereof are provided. The electronic device includes a DSP (Digital Signal Processor). The DSP receives a digital signal. The digital signal includes a plurality of frames. The DSP divides the plurality of frames into a vital group and a non-vital group according to a criterion. The DSP compares a total number of frames of the vital group with a threshold value. In response to the total number of frames of the vital group being greater than the threshold value, the DSP may calculate signal strength of the vital group.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 17, 2024
    Inventors: Chuan Yen KAO, Yu Wen HUANG, Wei Rong TSENG, Yao Tsung CHANG, Yin Yu CHEN
  • Publication number: 20240347669
    Abstract: A semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active structure. The active structure includes a first well set, a second well set and a plurality of barriers. The first well set is disposed on the first semiconductor structure and includes one or multiple first wells. The second well set is disposed between the first well set and the second semiconductor structure and includes one or multiple second wells. The plurality of barriers is arranged alternately with the one or multiple first wells and the one or multiple second wells. The first well has a first thickness. The second well has a second thickness different from the first thickness. The one or multiple first wells and the one or multiple second wells include AlxInyGa1?x?yN respectively, wherein 0?x?1, 0?y?1, 0?1?x?y<1.
    Type: Application
    Filed: April 12, 2024
    Publication date: October 17, 2024
    Inventors: Feng-Wen HUANG, Yueh-Chern LIN
  • Publication number: 20240347230
    Abstract: A low noise cable core and a manufacturing method thereof and a low noise cable using the same include an insulated conductor, a first type conductive layer, and a second type conductive layer. The insulated conductor includes a conductive core and an insulation layer encapsulating the conductive core. The first type conductive layer encapsulates the insulated conductor, and the second type conductive layer encapsulates the first type conductive layer. The first type conductive layer and the second type conductive layer are respectively formed by way of a first forming method and a second forming method different from the first forming method.
    Type: Application
    Filed: April 16, 2024
    Publication date: October 17, 2024
    Inventors: Yang Zhou, Wen-Cheng Wu, Shi-Wen Huang