Patents by Inventor Wen-Tsao Chen
Wen-Tsao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Patent number: 10290576Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer.Type: GrantFiled: January 3, 2018Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20180145025Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer.Type: ApplicationFiled: January 3, 2018Publication date: May 24, 2018Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9865534Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer, wherein a top surface of the metal structure is level with a top surface of the stress reduction layer.Type: GrantFiled: June 13, 2016Date of Patent: January 9, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9543152Abstract: The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride.Type: GrantFiled: July 2, 2014Date of Patent: January 10, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Hung Huang, Bo-Chang Su, Chih-Ho Tai, Wen-Tsao Chen, Kuan-Chi Tsai
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Publication number: 20160300794Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer, wherein a top surface of the metal structure is level with a top surface of the stress reduction layer.Type: ApplicationFiled: June 13, 2016Publication date: October 13, 2016Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9373675Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.Type: GrantFiled: February 6, 2012Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Chun Lin, Wen-Tsao Chen, Chih-Ho Tai, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 9373536Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: GrantFiled: December 20, 2013Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20160005805Abstract: The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Inventors: Ching-Hung HUANG, Bo-Chang SU, Chih-Ho TAI, Wen-Tsao CHEN, Kuan-Chi TSAI
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Publication number: 20140106563Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: ApplicationFiled: December 20, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Patent number: 8629559Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: GrantFiled: February 9, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20130207264Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20130200490Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.Type: ApplicationFiled: February 6, 2012Publication date: August 8, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Chun Lin, Wen-Tsao Chen, Chih-Ho Tai, Ming-Ray Mao, Kuan-Chi Tsai
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Publication number: 20030062911Abstract: A method and apparatus for detecting the AC component of a signal. The present invention, which uses with a digital multimeter in a DC mode allows the DC component of a signal to be detected simultaneously with the measurement of the signal without affecting the measurement precision of the signal, is most advantageous for use in situations where the presence of the AC component, and not its precise magnitude, is what needs to be known.Type: ApplicationFiled: October 3, 2001Publication date: April 3, 2003Inventors: Cheng-Yung Kao, Wen-Tsao Chen
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Patent number: 6429696Abstract: The present invention generally relates to a peak hold and calibration circuit, and more particularly, to a peak hold and calibration circuit for use in measuring the signals in a digital multi-meter implemented by using an integrated circuit (IC) and a capacitor, wherein said IC is connected to said capacitor; wherein said IC comprises an operational amplifier, and a switching circuit; wherein a first voltage is applied to one input terminal of said operational amplifier and the other input terminal of said operational amplifier is connected to the feedback network while the output terminal of said operational amplifier is connected to said switching circuit; wherein the output of said switching circuit is a second voltage and connected to said capacitor.Type: GrantFiled: February 8, 2000Date of Patent: August 6, 2002Inventors: Cheng-Yung Kao, Wen-Tsao Chen, Yung-Pin Lee