Patents by Inventor Wen-Tung Chen
Wen-Tung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190096747Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.Type: ApplicationFiled: November 29, 2018Publication date: March 28, 2019Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Publication number: 20180301526Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.Type: ApplicationFiled: June 25, 2018Publication date: October 18, 2018Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Patent number: 10008559Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.Type: GrantFiled: January 31, 2017Date of Patent: June 26, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Publication number: 20170316981Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.Type: ApplicationFiled: January 31, 2017Publication date: November 2, 2017Inventors: Hung-Hao Chen, Che-Cheng Chang, Horng-Huei Tseng, Wen-Tung Chen, Yu-Cheng Liu
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Publication number: 20170278921Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.Type: ApplicationFiled: January 31, 2017Publication date: September 28, 2017Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Publication number: 20170278742Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.Type: ApplicationFiled: January 13, 2017Publication date: September 28, 2017Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
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Publication number: 20130291445Abstract: A coating method on diamond abrasive grains is used to form a conductive film on diamond abrasive grains. The conductive film has chemical composition gradient giving the diamond abrasive grain an outwardly increasing electrical conductibility as a function of film thickness. The subsequent electroplating layer can therefore more effectively embed the modified diamond abrasive grains, whilst the adhesion/bonding strength between substrate (work piece for electroplating) and the diamond abrasive grains is improved.Type: ApplicationFiled: May 1, 2012Publication date: November 7, 2013Applicant: SIGMA INNOVATION TECHNOLOGY INC.Inventors: WEN-TUNG CHEN, JU-LIANG HE
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Patent number: 8437142Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first groove and the first connection slot. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove. The connection metal layer covers the under bump metallurgy layer to form a third groove, wherein the under bump metallurgy layer covers a first coverage area of the first polymer block and a second coverage area of the second polymer block and reveals a first exposure area of the first polymer block and a second exposure area of the second polymer block.Type: GrantFiled: June 20, 2011Date of Patent: May 7, 2013Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Shyh-Jen Guo, Wen-Tung Chen
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Publication number: 20120319271Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.Type: ApplicationFiled: June 20, 2011Publication date: December 20, 2012Inventors: Cheng-Hung Shih, Shyh-Jen Guo, Wen-Tung Chen
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Publication number: 20120318570Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first groove and the first connection slot. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove. The connection metal layer covers the under bump metallurgy layer to form a third groove, wherein the under bump metallurgy layer covers a first coverage area of the first polymer block and a second coverage area of the second polymer block and reveals a first exposure area of the first polymer block and a second exposure area of the second polymer block.Type: ApplicationFiled: June 20, 2011Publication date: December 20, 2012Inventors: Cheng-Hung Shih, Shyh-Jen Guo, Wen-Tung Chen
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Patent number: 8330280Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.Type: GrantFiled: June 20, 2011Date of Patent: December 11, 2012Assignee: Chipbond Technology CorporationInventors: Cheng-Hung Shih, Shyh-Jen Guo, Wen-Tung Chen
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Publication number: 20040207977Abstract: Computer mainframe structure with complex DC and AC power supply, including a housing and a co-used power supply module. The respective hardware units of the computer and the co-used power supply module are mounted in the housing. The co-used power supply module is composed of a power supply unit, a relay unit, an overcurrent protection and several sockets arranged on a predetermined section of the housing. By means of the co-used power supply module, DC and AC power can be directly supplied to both the units disposed in the housing and the external peripheral equipment. Also, the peripheral equipment can be synchronously turned on or off along with the computer mainframe.Type: ApplicationFiled: April 16, 2003Publication date: October 21, 2004Applicant: Key Mouse Electronic Enterprise Co., Ltd.Inventors: Peter Chen, Wen-Tung Chen
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Patent number: 6805739Abstract: A method of manufacturing a photo-catalyst including titanium dioxide and silicon dioxide is provided, wherein titanium dioxide is synthesized by a collosol gelatinization utilizing the water generated by the esterification of acid and alcohol to conduct a reaction of hydrolysis condensation. The silicon dioxide is synthesized by a collosol gelatinization by adding Si(OC2H5)4, n-C4H9OH and water or Si(OC2H5)4, (CH3)Si(OC2H5)3 and water.Type: GrantFiled: July 29, 2002Date of Patent: October 19, 2004Assignee: China Textile InstituteInventors: Lien-Hua Chiu, Wen-Tung Chen, Jan-An Guu, Jeffrey Chi-Sheng Wu, I-Hsiang Tseng, Chih-Hsien Chen
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Publication number: 20040016368Abstract: The present invention aims to provide a component and a method of manufacturing a photo-catalyst; this component includes titanium dioxide and silicon dioxide, wherein titanium dioxide is synthesized by a collosol gelatinization via utilizing the water generated by the esterification of acid and alcohol to conduct a reaction of hydrolysis condensation; the said silicon dioxide is synthesized by a collosol gelatinization via adding alkylaryl silane oxidized compounds; the photo-catalyst with these kinds of components is excellent in antifouling, sterilization, deodorization and can be efficiently applied to manufacturing raw material for textile fiber and coating textile products so as to make the manufactured textile products capable of antifouling, sterilizing and deodorizing.Type: ApplicationFiled: July 29, 2002Publication date: January 29, 2004Inventors: Lien-Hua Chiu, Wen-Tung Chen, Jan-An Guu, Jeffery Chi-Sheng Wu, I-Hsiang Tseng, Chih-Hsien Chen
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Patent number: 6302948Abstract: The present invention relates to a textile ink-jet printing-purpose disperse dye micro-emulsion agent, which uses dispersing agents such as sodium polynaphthalene formaldehyde sulfonates, surfactants such as POE NP ether, and silicone derivative emulsion-type defoaming agents and bactericidal fungicidal agents for ink-jet CMYK four-color disperse dyes forming a stable dye micro-emulsion through micro-jetting homogenized emulsifier. This invention focuses on the disperse dyes suitable for polymers, applying a low-cost environmentally protective micro-emulsion agent in the ink protection technology so that the O/W model becomes a stable and homogenized system. This gives the textile ink-jet printing-purpose disperse dye micro-emulsion agent, with a dye particle diameter lying below 300 nm and high storage stability, rinse, sublimation, and light fastness over 4.Type: GrantFiled: January 27, 2000Date of Patent: October 16, 2001Assignee: China Textile InstituteInventors: Cheng Kun Lin, Chong Yu Chen, Wen Tung Chen, Shiau Yin Peggy Chang
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Patent number: 6197920Abstract: The present invention relates to the synthesis of new type of diamine monomer, 1,3-bis(4-amonophenoxy)naphthalene, and with such a compound to produce a series of aromatic polymers, including polyamide, polyimide, copoly(amide-imide)s, etc., such polymers having excellent resistance to heat and mechanical properties.Type: GrantFiled: July 21, 1999Date of Patent: March 6, 2001Assignee: China Textile InstituteInventors: Kun Lin Cheng, Wen-Tung Chen
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Patent number: 6191214Abstract: The present invention consists of a method for the preparation of an anionic water dispersible polyurethane(PU), which has excellent adhesive properties. The preparation method involves the formation of prepolymer from polyisocyanates and an active hydrogen containing compound such as polyols, followed by chain extension with aliphatic diols or diamines, and finally by chain extension with N-(2-aminoalkyl-2-aminoethoxylate ethane sulfonate and dispersion of the reaction product by deionized water to obtain water-borne polyurethane adhesive.Type: GrantFiled: July 16, 1999Date of Patent: February 20, 2001Assignee: China Textile InstituteInventors: Kun Lin Cheng, Wen-Tung Chen
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Patent number: 5886131Abstract: A method for synthesizing 1,4-bis(4-aminophenoxy)naphthalene and a series of polyamides, polyimides and copoly(amide-imide)s derived from the said compound is disclosed. These polymers possess excellent thermal stability and mechanical strength.Type: GrantFiled: May 30, 1997Date of Patent: March 23, 1999Assignee: China Textile InstituteInventors: Shin Chuan Yao, Jongfu Wu, Kun-Lin Cheng, Wen-Tung Chen
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Patent number: 5863983Abstract: A blocked hydrophilic polyurethane with molecular weight of 500.about.40,000, 5.about.70% solid content and 5.about.200 milliequivalent per 100 g polymer of sulfonic acid salt, can be prepared from following reactants:a. Organic isocyanates;b. Polyols, including polyether polyol, polyester polyol, polycarbonate, and polycaprolactone, that can participate in the polyaddition reactions with isocyanates.c. Polyols containing sulfonate group.d. Organic blocking agents capable of reacting with isocyanates.The blocked hydrophilic PU resins formed from above reactants can be applied for the anti-wrinkle treatment of cellulosic textiles with excellent performance.Type: GrantFiled: August 25, 1997Date of Patent: January 26, 1999Assignee: China Textile InstituteInventors: Jongfu Wu, Cheng Kun Lin, Wen-Tung Chen
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Patent number: D756747Type: GrantFiled: November 6, 2014Date of Patent: May 24, 2016Assignee: TAIWAN FU HSING INDUSTRIAL CO., LTD.Inventors: Wen-Fa Wu, Wen-Tung Chen