Patents by Inventor Wen-Tung Yang

Wen-Tung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Input receiver and operation method thereof
    Patent number: 8773179
    Abstract: An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 8, 2014
    Assignee: Etron Technology, Inc.
    Inventors: Yi-Hao Chang, Shih-Hsing Wang, Wen-Tung Yang, Yen-An Chang
  • INPUT RECEIVER AND OPERATION METHOD THEREOF
    Publication number: 20130234766
    Abstract: An input receiver includes a first input receiving unit, a second input receiving unit, a delay unit, and a first logic unit. The first input receiving unit receives an inverse wake-up signal, an external clock enable signal, a first voltage, and a reference signal, and then generates a first enable signal according to the external clock enable signal and the reference signal. The second input receiving unit receives the external clock enable signal, the first voltage, and an inverse enable voltage, and then generates a second enable signal as its output according to the external clock enable signal. The delay unit generates a wake-up signal according to the second enable signal. The first logic unit receives the wake-up signal and the first enable signal, and then generates an internal clock enable signal according to the wake-up signal and the first enable signal.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 12, 2013
    Applicant: ETRON TECHNOLOGY, INC.
    Inventors: Yi-Hao Chang, Shih-Hsing Wang, Wen-Tung Yang, Yen-An Chang