Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A first processor identifies a target processor in response to the first processor executing a plurality of instructions in an instrumentation mode. The processor designates the target processor to execute instrumentation instructions associated with the plurality of instructions in response to identifying the target processor.

Abstract: A computer implemented method, apparatus and computer usable program code for marking instructions for instrumentation. A plurality of instructions is presented in a graphical user interface. A user input selecting a set of instructions in the plurality of instructions for instrumentation is received through the graphical user interface. A set of instructions is marked as a set of instrumentation instructions in response to receiving the user input. The set of instructions are executed by a processor if the processor is in an instrumentation mode, and the instrumentation instructions are unexecuted if an absence of the processor being in the instrumentation mode is present.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a processor is in instrumentation mode in response to the processor executing a plurality of instructions. When the determination is made that the processor is in instrumentation mode, instrumentation instructions associated with the plurality of instructions are executed. The instrumentation instructions are unexecuted in response to an absence of the processor being in instrumentation mode.

Abstract: A computer implemented method, apparatus and computer program product for processing instructions. A determination is made as to whether an instruction is a start instrumentation instruction in response to identifying the instruction for execution while executing the instructions using a normal set of processor resources in a processor. Subsequent instructions are executed using an alternate set of processor resources until an end instrumentation instruction is encountered.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a processor executing a plurality of instructions is in an instrumentation mode. The processor has a normal set of resources and an alternate set of resources in which the alternate set of resources is associated with the instrumentation mode. When a determination is made that the processor is in the instrumentation mode, the processor executes instrumentation instructions in the plurality of instructions using the alternate set of resources and executes all other instructions in the plurality of instructions using the normal set of resources.

Abstract: A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a set of instructions are a set of instrumentation instructions in response to identifying the set of instructions in instructions for execution. A further determination is made as to whether a processor executing the instructions is in an instrumentation mode if the set of instructions are instrumentation instructions. The processor executes the set of instrumentation instructions only if the processor is in the instrumentation mode.

Abstract: A computer implemented method, apparatus, and computer usable medium for gathering performance related data in a multiprocessing environment. Instrumentation code is executed on a processor that minimizes the distortion to the processor resources used to execute the program to be profiled. Data is written by the instrumentation code to a shared memory in response to an event occurring during execution of the program. The data is generated during execution of the program on the processor and the instrumentation code uses shared memory to convey the data to a profiling application running on a set of profiling processors. The data is collected by the set of profiling processors in the shared memory written by the instrumentation code.

Abstract: A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract: A method and apparatus are provided for efficiently managing hot spots in a resource managed computer system. The system utilizes a controller, a series of requester groups, and a series of loan registers. The controller is configured to allocate and is configured to reallocate resources among the requestor groups to efficiently manage the computer system. The loan registers account for reallocated resources such that intended preallocation of use of shared resources is closely maintained. Hence, the computer system is able to operate efficiently while preventing any single requestor or group of requesters from monopolizing shared resources.

Abstract: The present invention provides for a plurality of partitioned ways of an associative cache. A pseudo-least recently used binary tree is provided, as is a way partition binary tree, and signals are derived from the way partition binary tree as a function of a mapped partition. Signals from the way partition binary tree and the pseudo-least recently used binary tree are combined. A cache line replacement signal is employable to select one way of a partition as a function of the pseudo-least recently used binary tree and the signals derived from the way partition binary tree.

Abstract: Apparatus and method for compressing sequentially related data while fully preserving the informational content of the data. In a preferred form, digital format video image data individualized by pixel is compressed by defining a reference value for a first pixel position, encoding successive pixel values based on offsets from the reference value, and counting the pixels so encoded. Compression is obtained by having the bit count of the encoding be less than the original bit count associated with each pixel value. The reference value or encoding range is adjusted as necessary to retain the informational content of the original image data. The invention also find usage in a multimedia context, where the encoding is based upon a temporal relationship of single or multiple pixels. Full preservation of the original information content is retained throughout.