Patents by Inventor Wen Wei

Wen Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142034
    Abstract: A projection system, a projection device, and a control method thereof are provided. The control method of the projection device includes the following steps: transmitting a first original command by a terminal device; projecting an adjustment image by the projection device in response to the first original command corresponding to an image correction operation of the projection device, wherein the adjustment image includes at least one pattern array and at least one adjustment reference point; transmitting a second original command by the terminal device; and adjusting a position of the at least one adjustment reference point of the adjustment image by the projection device in response to the second original command corresponding to adjusting the position of the at least one adjustment reference point of the adjustment image, wherein the at least one adjustment reference point is located in the corresponding at least one pattern array.
    Type: Application
    Filed: October 24, 2024
    Publication date: May 1, 2025
    Applicant: Coretronic Corporation
    Inventors: Chih-Yi Chung, Ssu-Ming Chen, Hsin-Ya Lai, Wen-Wei Tsai
  • Patent number: 12271207
    Abstract: A method for controlling a plurality of autonomous robots for performing environment maintenance operations includes: generating a setup command that indicates a selected location, a plurality of selected robots, an available time slot, and a distribution mode signal that indicates whether the selected robots are to be controlled based on the available time slot or an inputted priority section; and generating a plurality of sub-routes based on different parameters, depending on the distribution mode signal. The sub-routes are generated to be connected into an unbroken trail. Then, the sub-routes are transmitted to the selected robots, respectively, so as to control each of the selected robots to move along the respective one of the sub-routes.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: April 8, 2025
    Assignee: URSrobot AI Inc.
    Inventors: Chien-Tung Chen, Chung-Hou Wu, Chao-Cheng Chen, Wen-Wei Chiang, Yi-Jin Lin
  • Patent number: 12266421
    Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: April 1, 2025
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wen-Wei Lin, Ching-Sheng Cheng
  • Publication number: 20250105169
    Abstract: A semiconductor package includes a semiconductor die, an interposer disposed below the semiconductor die, first joints electrically coupling the semiconductor die to the interposer, at least one second joint coupling the semiconductor die to the interposer, and a first underfill disposed between the semiconductor die and the interposer to surround the active and second joints. The semiconductor die includes a first region, a seal ring region surrounding the first region, and a second region between the seal ring region and a die edge. The first joints are located within the first region, and the second joint is disposed at a die corner within the second region and is electrically floating in the semiconductor package.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Leu-Jen Chen, Wen-Wei Shen, Kuan-Yu Huang, Yu-Shun Lin, Sung-Hui Huang, Hsien-Pin Hu, Shang-Yun Hou
  • Publication number: 20250063802
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first transistor region and a second transistor region and then forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, in which the first gate structure includes a first hard mask, the second gate structure includes a second hard mask, and the first hard mask and the second hard mask have different thicknesses. Next, a patterned mask is formed around the first gate structure and the second gate structure, and then part of the first hard mask is removed.
    Type: Application
    Filed: September 13, 2023
    Publication date: February 20, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Wen Wei Wang, Xiang Xiang Zhou, Xiang Wang, Hailong Gu, Wen Yi Tan
  • Publication number: 20250054144
    Abstract: Immune context scores are calculated for tumor tissue samples using continuous scoring functions. Feature metrics for at least one immune cell marker are calculated for a region or regions of interest, the feature metrics including at least a quantitative measure of human CD3 or total lymphocyte counts. A continuous scoring function is then applied to a feature vector including the feature metric and at least one additional metric related to an immunological biomarker, the output of which is an immune context score. The immune context score may then be plotted as a function of a diagnostic or treatment metric, such as a prognostic metric (e.g. overall survival, disease-specific survival, progression-free survival) or a predictive metric (e.g. likelihood of response to a particular treatment course). The immune context score may then be incorporated into diagnostic and/or treatment decisions.
    Type: Application
    Filed: October 19, 2024
    Publication date: February 13, 2025
    Inventors: Michael Barnes, Joerg Bredno, Rebecca C. Bowermaster, Srinivas Chukka, Wen-Wei Liu, Kandavel Shanmugam, Junming Zhu
  • Publication number: 20250056853
    Abstract: A junction field effect transistor device includes a substrate, a well region, a first top layer, a plurality of source/drain regions, a first isolation structure, a gate, and a plurality of first well slots. The substrate has a first conductivity type. The well region is embedded in the substrate. The well region has a second conductivity type. The first top layer is embedded in the well region. The first top layer has the first conductivity type. The source/drain regions are disposed on a top surface of the well region. The first isolation structure is adjacent to one of the source/drain regions. The gate is disposed on a top surface of the first top layer. The first well slots are disposed below the gate. A second-conductivity-type dopant concentration of the first well slots is lower than a second-conductivity-type dopant concentration of the well region.
    Type: Application
    Filed: September 25, 2023
    Publication date: February 13, 2025
    Inventors: Wen-Wei LAI, Wu-Te WENG
  • Publication number: 20250038744
    Abstract: A device including a first circuit, a second circuit, and a third circuit. The first circuit to receive a first signal and a second signal, and the first circuit to provide a third signal. The second circuit to receive a fourth signal and a fifth signal, and the second circuit to provide a sixth signal. The third circuit to receive the third signal and the sixth signal, and the third circuit to provide a seventh signal to indicate whether to track a difference between an amount of voltage provide to a driver and an amount of voltage provided by the driver or track a difference between an amount of voltage provided by a source and the amount of voltage provided to the driver.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Feng Su, Yue HU, Tom W. Kwan, Guo Wen Wei, Fang Lin, Iuri Mehr
  • Publication number: 20250038710
    Abstract: A device including a first circuit, a second circuit. The first circuit to receive a first signal, a second signal, and a third signal, and the first circuit to provide a fourth signal and a fifth signal. The second circuit to receive the fourth signal and the fifth signal, and the second circuit to control a first set of components to maintain a difference between a first amount of power provided to a first terminal of a driver and a second amount of power provided to a second terminal of the driver or to control a second set of components to maintain the difference between the first amount of power provided to the first terminal of the driver and the second amount of power provided to the second terminal of the driver.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Feng Su, Tom W. Kwan, Iuri Mehr, Fang Lin, Guo Wen Wei, Kevin Yuhang Li, Yue HU
  • Patent number: 12208365
    Abstract: A gene chip includes a chip carrier, a plurality of DNA nanoballs assembled on the chip carrier, and a polymer film formed on the chip carrier and wrapping the DNA nanoballs. The polymer film includes at least one of a film of a positively charged polymer, a film of a positively charged polymer which is modified, a film of a zwitterionic polymer, and a composite polymer film. The composite polymer film is formed by a layer-by-layer self-assembly process of a positively charged polymer and a negatively charged polymer. The gene chip has good sequencing quality and different functions can be achieved by coating with different polymers, such as the chip surface rapidly drying out and surface non-specific adsorption. A method of preparing a gene chip is further disclosed.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: January 28, 2025
    Assignee: BGI SHENZHEN
    Inventors: Zhao-Hui Wang, Hui Wang, Cheng-Mei Xing, Han-Dong Li, Wen-Wei Zhang, Jay Willis Shafto, Mei-Hua Gong, Jin Yang, Yin-Ling Luo, Zhen-Hua Zhang, Yuan Li, Xue-Qin Jiang
  • Publication number: 20250017938
    Abstract: Therapeutic combinations of fatty acid synthesis modulators and thyroid hormone receptor agonists are provided. The combinations may be used to treat disorders including metabolic disorders and liver disorders, such as nonalcoholic steatohepatitis/metabolic dysfunction-associated steatohepatitis (NASH/MASH).
    Type: Application
    Filed: June 20, 2024
    Publication date: January 16, 2025
    Inventors: Anne-Marie O'Farrell, George Kemble, Wen-Wei Tsai
  • Publication number: 20240427935
    Abstract: The present disclosure provides a method and an electronic apparatus for masking data on an electronic document. The method is performed by the electronic apparatus and includes: displaying the electronic document on a user interface; causing at least one analysis module to perform at least one analysis on the electronic document and a plurality of strings of the electronic document and output a first string among the plurality of strings and first position information associated with the first string according to a result of the at least one analysis; obtaining the first string and the first position information from the at least one analysis module; and generating, based on the first position information and the first string, a first masking object to mask the first string on the electronic document.
    Type: Application
    Filed: June 21, 2024
    Publication date: December 26, 2024
    Inventors: KANG-HUA HE, Yu-Chi Chen, Chia-Ting Lee, Wen-Wei Lin, Ching-Yi Chiang, Hsin-Yu Huang, Chun-Chin Su, Po-Chou Su, Sin-Jie Wang, Tso-Kuan Lee, Kai-Lin Shih
  • Publication number: 20240405121
    Abstract: The present disclosure provides a split gate MOSFET and a manufacturing method thereof. An epitaxy layer with a first conductivity type is formed on a substrate. A plurality of trenches are formed in the epitaxy layer. Impurities with a second conductive type is implanted and driven to the trenches to form a plurality of first doping areas. Since the first doping areas and none-doping areas of the epitaxy layer are alternately arranged with each other, and the first conductive type and the second conductive type are different conductivity types selected from P type or N type, the split gate MOSFET including the super junction structure is manufactured, and the advantages of simplifying manufacturing process, reducing cost and greatly reducing the on-resistance are achieved.
    Type: Application
    Filed: January 25, 2024
    Publication date: December 5, 2024
    Inventors: Chia-Ming Kou, Cin-Hua Jheng, Wen-Wei Shih, Cheng-Wei Hsu, Hsien-Yi Cheng
  • Patent number: 12154275
    Abstract: Immune context scores are calculated for tumor tissue samples using continuous scoring functions. Feature metrics for at least one immune cell marker are calculated for a region or regions of interest, the feature metrics including at least a quantitative measure of human CD3 or total lymphocyte counts. A continuous scoring function is then applied to a feature vector including the feature metric and at least one additional metric related to an immunological biomarker, the output of which is an immune context score. The immune context score may then be plotted as a function of a diagnostic or treatment metric, such as a prognostic metric (e.g. overall survival, disease-specific survival, progression-free survival) or a predictive metric (e.g. likelihood of response to a particular treatment course). The immune context score may then be incorporated into diagnostic and/or treatment decisions.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: November 26, 2024
    Assignee: Ventana Medical Systems, Inc.
    Inventors: Michael Barnes, Joerg Bredno, Rebecca C. Bowermaster, Srinivas Chukka, Wen-Wei Liu, Kandavel Shanmugam, Junming Zhu
  • Publication number: 20240387311
    Abstract: Semiconductor package includes interposer, dies, encapsulant. Each die includes active surface, backside surface, side surfaces. Backside surface is opposite to active surface. Side surfaces join active surface to backside surface. Encapsulant includes first material and laterally wraps dies. Dies are electrically connected to interposer and disposed side by side on interposer with respective backside surfaces facing away from interposer. At least one die includes an outer corner. A rounded corner structure is formed at the outer corner. The rounded corner structure includes second material different from first material. The outer corner is formed by backside surface and a pair of adjacent side surfaces of the at least one die. The side surfaces of the pair have a common first edge. Each side surface of the pair does not face other dies and has a second edge in common with backside surface of the at least one die.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou, Kuan-Yu Huang
  • Patent number: 12148678
    Abstract: Semiconductor package includes interposer, dies, encapsulant. Each die includes active surface, backside surface, side surfaces. Backside surface is opposite to active surface. Side surfaces join active surface to backside surface. Encapsulant includes first material and laterally wraps dies. Dies are electrically connected to interposer and disposed side by side on interposer with respective backside surfaces facing away from interposer. At least one die includes an outer corner. A rounded corner structure is formed at the outer corner. The rounded corner structure includes second material different from first material. The outer corner is formed by backside surface and a pair of adjacent side surfaces of the at least one die. The side surfaces of the pair have a common first edge. Each side surface of the pair does not face other dies and has a second edge in common with backside surface of the at least one die.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou, Kuan-Yu Huang
  • Publication number: 20240363587
    Abstract: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou
  • Patent number: 12099177
    Abstract: A lens-free microscopic imaging system (11), which is used to image microbeads (15) with pattern codes, includes an illumination system (11a) and an imaging system (11b). The illumination system (11a) includes an illumination light source (111) and an excitation light source (112). The imaging system (11b) includes an image sensor (113). The illumination light source (111) is used to emit illumination light to irradiate the microbeads (15), causing the irradiated microbeads (15) to be imaged on the image sensor. The excitation light source (112) is used to emit excitation light to excite the microbeads (15) to generate specific signals. The image sensor (113) is used to collect the images of the microbeads (15) and the specific signals to generate images. The imaging system (11) does not require a lens system. The present disclosure improves a detection efficiency of the microbeads (15).
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: September 24, 2024
    Assignee: BGI SHENZHEN
    Inventors: Qing Xie, Wei-Mao Wang, Wen-Wei Zhang, Mengzhe Shen
  • Publication number: 20240310972
    Abstract: A planning method for a displaying device, comprising: read and decode a device description file with a host of a planning system; display a planning interface on a screen via the host; take an object configuration step to configure at least one graphical object to the at least one display page and set an object parameter of the at least one graphical object; generate a corresponding graphical user interface configuration file via the host. When the planning system is connected to the displaying device, the host transmits the graphical user interface configuration file to the displaying device. A microcontroller of the displaying device displays a corresponding graphical user interface on the displaying module based on the graphical user interface configuration file. In this way, the operation time for the user to plan the graphical user interface could be effectively saved.
    Type: Application
    Filed: August 8, 2023
    Publication date: September 19, 2024
    Applicant: WINSTAR DISPLAY CO., LTD.
    Inventors: YU-PIN LIAO, CHIEN-CHOU HSU, CHIA-HSIANG NI, WEN-WEI CHUNG, SSU-TSUNG CHEN, YING-SHUN LIAO, YEN-HUA LIAO
  • Publication number: 20240312967
    Abstract: A display panel including a substrate, a light-emitting device, a light-shielding layer, and a light-guide pillar is provided. The light-emitting device is disposed on the substrate. The light-shielding layer is disposed on the substrate and has a sidewall surrounding an opening. The light-guide pillar is disposed between the substrate and the light-emitting device and located in the opening. A gap exists between the light-guide pillar and the sidewall of the light-shielding layer.
    Type: Application
    Filed: May 27, 2024
    Publication date: September 19, 2024
    Applicant: AUO Corporation
    Inventors: Fang-Cheng Yu, Wen-Wei Yang, Cheng-Yeh Tsai