Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Abstract: For a printed circuit board assembly (“PCBA”) selected electronic components are highlighted on a graphic representation of the PCBA on a display of a computer system. The components are selected responsive to temperature and time limits of the selected components. Ones of the highlighted components are associated to respective temperature sensors on the PCBA. Responsive to where the one or more additional ones of the highlighted components are located on the PCBA relative to the at least one of the respective temperature sensors, one or more additional ones of the highlighted components are associated with at least one of the respective temperature sensors. The computer system receives data for respective signals indicating temperatures encountered by the respective temperature sensors when the PCBA is heated in a manufacturing process. The computer system shows whether any of the time and temperature limits were exceeded during the manufacturing process.

Abstract: For a printed circuit board assembly (“PCBA”) selected electronic components are highlighted on a graphic representation of the PCBA on a display of a computer system. The components are selected responsive to temperature and time limits of the selected components. Ones of the highlighted components are associated to respective temperature sensors on the PCBA. Responsive to where the one or more additional ones of the highlighted components are located on the PCBA relative to the at least one of the respective temperature sensors, one or more additional ones of the highlighted components are associated with at least one of the respective temperature sensors. The computer system receives data for respective signals indicating temperatures encountered by the respective temperature sensors when the PCBA is heated in a manufacturing process. The computer system shows whether any of the time and temperature limits were exceeded during the manufacturing process.

Abstract: A method for printed circuit board design of temperature sensitive components includes a scrub tool receiving a list of part numbers for electronic components of a printed circuit board assembly (“PCBA”). The scrub tool sends one or more queries for finding temperature and time limits of the electronic components to a database. A mapping tool receives a selection of one or more part numbers responsive to the one or more queries, wherein the selection is responsive to the temperature and time limits. The mapping tool sends a data structure to a physical design tool which is configured with physical design data for generating a graphic representation of the PCBA. The data structure from the mapping tool provides the received selection of one or more part numbers and configures the physical design tool to highlight components having part numbers of the selection on the PCBA graphic representation.

Abstract: A method for printed circuit board design of temperature sensitive components includes a scrub tool receiving a list of part numbers for electronic components of a printed circuit board assembly (“PCBA”). The scrub tool sends one or more queries for finding temperature and time limits of the electronic components to a database. A mapping tool receives a selection of one or more part numbers responsive to the one or more queries, wherein the selection is responsive to the temperature and time limits. The mapping tool sends a data structure to a physical design tool which is configured with physical design data for generating a graphic representation of the PCBA. The data structure from the mapping tool provides the received selection of one or more part numbers and configures the physical design tool to highlight components having part numbers of the selection on the PCBA graphic representation.