Abstract: A method of accessing a trusted platform module in a computing device is disclosed. The method includes storing a platform authorization key in a memory of the computing device that includes the trusted platform module. The platform authorization key includes permitting access to the trusted platform module. The method includes obtaining a digital signature in response to the computing device requesting access to the trusted platform module. The digital signature is generated using at least a command for configuring the trusted platform module. The method includes verifying the digital signature and allowing retrieval of the platform authorization key from the memory of the computing device in order to access the trusted platform module in response to the digital signature is verified, and denying retrieval of the platform authorization key otherwise.

Abstract: An electrical connector, including an insulating body; multiple first terminals, insert molded into the insulating body and having at least one grounding terminal, at least one power supply terminal and a pair of differential signal terminals located between the grounding terminal and the power supply terminal adjacent to each other; and a middle shielding sheet, insert molded into the insulating body, and located above or below the first terminals. The middle shielding sheet has, on at least one side of a central line of the middle shielding sheet, a notch and a first protruding portion away from the central line as compared to the notch. The central line extends in a front-rear direction. The notch is concavely provided backward from a front end edge of the middle shielding sheet, and vertically corresponds to the power supply terminal. The first protruding portion has a through-hole vertically corresponding to the grounding terminal.

Abstract: A dual-sided display is disclosed, including a substrate, a first active device, a first micro light emitting device, a patterned photoresist layer, a reflective electrode, a second micro light emitting device, a protective layer, and a first conductive electrode. The first micro light emitting device is disposed on the substrate and electrically connected to the first active device. The patterned photoresist layer is disposed on the substrate and covers a portion of the first micro light emitting device. The reflective electrode covers the patterned photoresist layer and a portion of the substrate. The second micro light emitting device is disposed on the reflective electrode. The protective layer covers the reflective electrode and a portion of the second micro light emitting device. The first conductive electrode covers the protective layer and is electrically connected to the second micro light emitting device.

Abstract: The present disclosure relates to a panel control system and an editing method thereof. The panel control system includes a display panel and a processing device connected to the display panel. The processing device includes a graphical user interface (GUI) program, including an interface element window which includes a plurality of interface elements, and an interface editing window connected to the interface element window. Each of the interface elements includes an element command window, an element parameter window, and an element attribute window. The element command window includes a plurality of original element commands. The plurality of the original element commands are dragged to the element parameter window to form a plurality of element parameter commands. The element attribute window includes a plurality of element attribute commands.

Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits that include memory chips and a memory buffer. One or more processors identify a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits. The processor(s) identify a location and address of each memory chip in the identified failed integrated circuits that has a memory chip failure. The processor(s) identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Abstract: The present invention provides an electronic device and a method for fabricating the same. The electronic device includes a driving-circuit substrate, light-emitting elements, an optical layer, and an adhesive layer. The light-emitting elements are disposed on the driving-circuit substrate, and the optical layer is disposed on the light-emitting elements. The adhesive layer is disposed between the optical layer and the light-emitting elements. The optical layer includes a first surface and a second surface that are opposite to each other. The first surface of the optical layer has a plurality of first convex lens structures, and at least a part of the first convex lens structures are at least partially overlapped with the light-emitting elements in the vertical projection direction.

Abstract: The present invention provides a magnetophorisis measuring system, comprising a microscope device, a magnetic field generator, an image capturing unit, and a processing unit. The microscope device is utilized to magnify a sample liquid having a plurality of objects respectively having a plurality of magnetic particles. The magnetic field generator is utilized to provide an external magnetic field on the sample liquid such that the objects are moved by the external magnetic field. The image capturing unit is utilized to capture a dynamic image with respect to the fluid sample in a view field of the microscope device. The processing unit receives the dynamic image, automatically detects and locks moving objects, determines a motion status corresponding to each object, and quantifies the magnetic particles according to motion status of each object.

Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Abstract: A system and method for providing content to a user based on at least one prior user experience are provided. First content is transmitted to a user, wherein at least some of the first content is transmitted in response to one or more user content selections. Frequency information based on the inputs and/or the first content is stored. A request for content is received from the user. Second content is selected based on the frequency information.

Abstract: The present invention provides an electronic device and a method for fabricating the same. The electronic device includes a driving-circuit substrate, light-emitting elements, an optical layer, and an adhesive layer. The light-emitting elements are disposed on the driving-circuit substrate, and the optical layer is disposed on the light-emitting elements. The adhesive layer is disposed between the optical layer and the light-emitting elements. The optical layer includes a first surface and a second surface that are opposite to each other. The first surface of the optical layer has a plurality of first convex lens structures, and at least a part of the first convex lens structures are at least partially overlapped with the light-emitting elements in the vertical projection direction.

Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.

Abstract: Provided are a metallic crosslinking coagent, preparation methods thereof, and a resin composition comprising the metallic crosslinking coagent. With the active-hydrogen containing organic phosphorus compound group and metallophilic acrylate group, the metallic crosslinking coagent provides both stabilizer and flame-retardant effects, enhances the crosslinking efficiency of the resin composition, and improves the compatibility between flame retardant and the polymer. Accordingly, the metallic crosslinking coagent is effective to improve the mechanical properties of the application material and to develop a safe and environmentally friendly flame retardant material.

Abstract: A light emitting device including a first semiconductor layer, a light emitting layer, a second semiconductor layer, a first electrode, and a second electrode is provided. The light emitting layer is deposited between the first and the second semiconductor layers. The first semiconductor layer, the light emitting layer and the second semiconductor layer form a stepped structure including a first electrode connection surface, a second electrode connection surface, and a connection portion. The first electrode connection surface is located on the first semiconductor layer. The second electrode connection surface is located on the second semiconductor layer. The connection portion connects the first and the second electrode connection surfaces. The connection portion includes a first surface, a second surface, and a third surface. A first corner s formed between the first and the second surfaces. A second corner is formed between the second and the third surfaces.

Abstract: A bi-directional optical module includes a substrate, at least one first light-emitting diode (LED), and at least one second LED. The first LED is disposed on a surface of the substrate. The first LED has a first reflection surface and a first light-outlet surface that are opposite to each other, and the first light-outlet surface is away from the substrate relative to the first reflection surface. The second LED is disposed on the same surface of the substrate. The second LED has a second reflection surface and a second light-outlet surface that are opposite to each other, and the second light-outlet surface is close to the substrate relative to the second reflection surface. The substrate has at least one light-transparent area that is not occupied by the first LED and the second LED.

Abstract: A dual-sided display is disclosed, including a substrate, a first active device, a first micro light emitting device, a patterned photoresist layer, a reflective electrode, a second micro light emitting device, a protective layer, and a first conductive electrode. The first micro light emitting device is disposed on the substrate and electrically connected to the first active device. The patterned photoresist layer is disposed on the substrate and covers a portion of the first micro light emitting device. The reflective electrode covers the patterned photoresist layer and a portion of the substrate. The second micro light emitting device is disposed on the reflective electrode. The protective layer covers the reflective electrode and a portion of the second micro light emitting device. The first conductive electrode covers the protective layer and is electrically connected to the second micro light emitting device.

Abstract: The present invention is related to a method for detecting a protein comprising: (1) providing a fusion protein, wherein the fusion protein comprises the protein which is fused with a secondary antibody detected protein tag, wherein the secondary antibody detected protein tag comprises at least one epitope selected from the Fc region of at least one primary antibody which is capable of being detected by a corresponding secondary antibody; (2) contacting the fusion protein with a secondary antibody which binds to the secondary antibody detected protein tag to form a protein/antibody complex; and (3) detecting the protein/antibody complex.

Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.

Abstract: A method for inspecting a vehicle includes acquiring a unique identity number of an insepected vehicle, carrying out X-ray scanning on the inspected vehicle to acquire an X-ray image of the inspected vehicle, retrieving at least one historical inspected image related to the unique identity number from a historical inspection database, determining, based on one template image selection algorithm selected from multiple template image selection algorithms, one of the at least one historical inspected images as a template image, determining a difference region between the X-ray image and the template image, and presenting the difference region to a user.

Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage.

Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.