Abstract: The disclosure relates to the technical field of network communication, in particular to a method and an apparatus for inter-communication between L2 and L3 VPNs. The method is applied to Provider Edge-Aggregation (PE-AGG) equipment, which comprises a physical interface of a PW of L2 VPN, a physical interface of a public network of L3 VPN, L2 VE and L3 VE logical interfaces.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A semiconductor device includes a gate structure on a substrate, a source/drain region adjacent to the gate structure, an interlayer dielectric (ILD) layer around the gate structure, a contact plug in the ILD layer and adjacent to the gate structure, an air gap around the contact plug, a barrier layer on and sealing the air gap, a metal layer on the barrier layer, a stop layer adjacent to the barrier layer and on the ILD layer, and an inter-metal dielectric (IMD) layer on the ILD layer. Preferably, bottom surfaces of the barrier layer and the stop layer are coplanar and top surfaces of the IMD layer and the barrier layer are coplanar.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

Abstract: A system may port a data model into a strict schema system, translate the data model into a transformation rule definition, fit the transformation rule definition to a transform action, receive strict schema data, perform the transform action on the strict schema data based on the transformation rule definition to form rough data, and execute filtering and enriching operations on the rough data to form loose schema data.

Abstract: A computed tomography (CT) machine system and a state monitoring method are described. The CT machine system comprises a drum-shaped component, a 3D camera, and a control system. The drum-shaped component comprises a cylindrical body, with the center of the cylindrical body being provided with a hollow portion which is rotationally symmetrical about the central axis of the cylindrical body, a rotating component disposed in the cylindrical body rotating about the central axis, a plurality of trigger marks arranged in the rotating component, and a window provided in the cylindrical body. The 3D camera generates image data that is transferred to the control system, from which the control system determines state data of the CT machine. The 3D camera captures an image of the trigger marks through the window to generate marked image data.

Abstract: An antimicrobial peptide (AMP) or peptide derivative, a substitute for the AMP or peptide derivative, an AMP or peptide derivative composition, and a preparation method and application of the AMP or peptide derivative composition. The AMP or peptide derivative includes at least one selected from the group consisting of amino acid sequences I and II: where Xa1, Ba1, U1, Za1, Ba2, Xa2, Ba3, Za2, Ba4, Xa3, Xb1, Bb1, Ca1, Zb1, Bb2, Xb2, Bb3, Zb2, Bb4, Xb3, and Ca2 each are independently selected from the group consisting of natural amino acids (NAAs) and unnatural amino acids (UAAs). The AMP or peptide derivative provided by the present application can combine with a lipid structure of a cell wall/membrane to damage its physical and chemical properties, thereby destroying the microbial wall/membrane to kill microorganisms and tumor cells.

Abstract: Disclosed herein is a water-borne coating composition including a) at least one water-soluble or water-dispersable binder, and b) at least one sagging control agent (SCA) that is obtained by reaction of b1) at least one aliphatic polyisocyanate and b2) at least one amine selected from a group consisting of C1-C10-alkoxy-C1-C10-alkylamine, di-C1-C10-alkoxy-C1-C10-alkylamine, C4-C10-alkyl substituted aniline and di-C4-C10-alkyl substituted aniline in the presence of Component a). Further disclosed herein is a method of preparing the coating composition.

Abstract: An example operation may include one or more of storing log files via a data store, comparing a test log file from the data store which is generated from tests performed on source code in a test environment to a productive log file from the data store that is generated by executing the source code in a productive environment, identifying one or more components of the source code that are not covered by the tests based on the comparison, and generating a visualization which includes identifiers of the one or more components that are not covered by the tests and display the visualization via a user interface.

Abstract: An approach is disclosed that receives an incoming data record, the data record including a number of data fields. The approach determines a current Real-Time Resources Score (RTRS). The RTRS being a forecast of the information handling system's ability to handle incoming data transmissions. When the RTRS is lower than a current data accumulation rate, a subset of the data record is sent based on field priorities. The approach assigns priorities to each of the data fields included in the data record based on a priority assessment of the respective data fields. The approach then sends, to a data receiver, a subset of the plurality of data fields based on the assigned priority.

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

Abstract: An air freight rate data caching method and system. The method includes converting air freight rate data into a data format of a first-level cache, and storing same in the first-level cache; performing, on the basis of a flight origin city and a flight destination city, data fragmentation on the air freight rate data stored in the first-level cache so as to generate fragmented data; and storing the fragmented data, after same is validated, in a second-level cache. Each data node of the fragmented data cached in the second-level cache only includes part of the air freight rate data on which a fragmentation algorithm can be performed, and therefore, the horizontal expansion capacity of a cache system is improved relative to the case where cached data copies are all complete sets.

Abstract: A power consumption reduction method can include defining y operation scenarios according to x types of extracted information, generating z power profiles each used for controlling power provided to a subset of a plurality of processors, assigning the z power profiles to the y operation scenarios in a machine learning model, collecting to-be-evaluated information by the plurality of processors, comparing the to-be-evaluated information with the x types of extracted information to find a most similar type of extracted information, using the machine learning model to select an optimal power profile from the z power profiles according to the most similar type of extracted information, and applying the optimal power profile to control the power provided to the subset of the plurality of processors. The subset of the plurality of processors are of the same type of processor. x, y and z can be an integer larger than zero.

Abstract: The present disclosure relates to a light energy collecting system and a detection apparatus. Some embodiments of the present disclosure provide a light energy collecting system and a detection apparatus, to correct chromatic aberration, simplify system structure, and improve system reliability and stability.

Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.

Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.

Abstract: A magnetoresistive random access memory (MRAM) structure is provided in the present invention, including multiple MRAM cells, and an atomic layer deposition dielectric layer between and at outer sides of the MRAM cells, wherein the material of top electrode layer is titanium nitride, and the nitrogen percentage is greater than titanium percentage and further greater than oxygen percentage in the titanium nitride, and the nitrogen percentage gradually increases inward from the top surface of top electrode layer to a depth and then start to gradually decrease to a first level and then remains constant, and the titanium percentage gradually decreases inward from the top surface of top electrode layer to the depth and then start to gradually increase to a second level and then remains constant.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.