Patents by Inventor Wen-Wen Gong

Wen-Wen Gong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230025163
    Abstract: A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.
    Type: Application
    Filed: August 17, 2021
    Publication date: January 26, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Wen Wen Gong, Xiaofei Han, Chow Yee Lim, Hong Liao, Jun Qian
  • Patent number: 9922832
    Abstract: A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region surrounding the first region; forming a gate stack and a dummy gate stack in the first region, wherein the dummy gate stack surrounds the gate stack; forming an oxide layer on an exterior wall and a top surface of the dummy gate stack; forming a dummy conductive layer on the gate stack, the dummy gate stack and the oxide layer, wherein the dummy conductive layer has a concave bowl-shaped top surface in the first region; and performing a chemical mechanical polishing (CMP) process on the dummy conductive layer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: March 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Xiao-Fei Han, Ju-Bao Zhang, Chao Jiang, Hong Liao, Wen-Wen Gong