Patents by Inventor Wen-Yao Chang

Wen-Yao Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087592
    Abstract: A package structure includes a first bonding film on a first package component and a first alignment mark in the first bonding film. The first alignment mark includes a plurality of first patterns spaced apart from each other. The package structure includes a second bonding film on a second package component and bonded to the first bonding film, and a second alignment mark in the second bonding film. The second alignment mark includes a plurality of second patterns spaced apart from each other, and the first patterns overlap the second patterns. In this case, an interference pattern can be formed by the optical signal passing through the varying spacing between the gratings of top wafer and bottom wafer due to pitch difference between first pitch and second pitch. By reading the optical signal, the resolution of overlay (misalignment) measurement is improved.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Geng-Ming CHANG, Kewei ZUO, Tzu-Cheng LIN, Chih-Hang TUNG, Wen-Chih CHIOU, Wen-Yao CHANG, Chen-Hua YU
  • Patent number: 12237288
    Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
  • Publication number: 20250015920
    Abstract: A transmitter for wireless communications includes an encoder, a normalizer, a binarizer, and a radio frequency (RF) circuit. The encoder is configured to encode a control message into a channel dimensional vector according to a channel dimension and the number of semantic fields by utilizing a training model. The control message includes at least one of control plane media access control layer information and control plane physical layer information. The normalizer is configured to normalize the channel dimensional vector to generate a normalized channel dimensional vector. The binarizer is configured to binarize the normalized channel dimensional vector to generate a fixed-point number. The RF circuit is configured to modulate the fixed-point number into an RF signal and transmit the RF signal.
    Type: Application
    Filed: November 14, 2023
    Publication date: January 9, 2025
    Inventors: Hsien Tsung HSU, Pei Yu HUNG, Wen-Yao CHANG
  • Patent number: 11990443
    Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
  • Publication number: 20230387058
    Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
  • Patent number: 11489947
    Abstract: A relay node and method for encapsulating a packet based on a tunneling protocol. The relay node includes a communication device, a storage device, and a processor. The communication device communicates with a receiving node and a transmitting node; the storage device stores multiple instructions; and the processor is coupled to the communication device and the storage device for loading and executing the multiple instructions stored in the storage device to: control the communication device to receive a packet transmitted by the transmitting node; generate a protocol header related to the packet based on the packet, and calculate a checksum as a checksum block in the multiple sections using multiple sections in the protocol header at least; generate an encapsulated packet including the protocol header and the packet; and transmit the encapsulated packet to the receiving node through the communication device for verifying the checksum block.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: November 1, 2022
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jing-Ping Wang, Wen-Yao Chang
  • Publication number: 20220141321
    Abstract: A relay node and method for encapsulating a packet based on a tunneling protocol. The relay node includes a communication device, a storage device, and a processor. The communication device communicates with a receiving node and a transmitting node; the storage device stores multiple instructions; and the processor is coupled to the communication device and the storage device for loading and executing the multiple instructions stored in the storage device to: control the communication device to receive a packet transmitted by the transmitting node; generate a protocol header related to the packet based on the packet, and calculate a checksum as a checksum block in the multiple sections using multiple sections in the protocol header at least; generate an encapsulated packet including the protocol header and the packet; and transmit the encapsulated packet to the receiving node through the communication device for verifying the checksum block.
    Type: Application
    Filed: November 27, 2020
    Publication date: May 5, 2022
    Inventors: Jing-Ping WANG, Wen-Yao CHANG
  • Publication number: 20220052009
    Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.
    Type: Application
    Filed: April 9, 2021
    Publication date: February 17, 2022
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shang-Yun Hou, Shu Chia Hsu, Yu-Yun Huang, Wen-Yao Chang, Yu-Jen Cheng
  • Publication number: 20200163209
    Abstract: A circuit board with a substrate made of silicone comprises a silicone substrate made of silicone; an adhering layer adhered on the silicone substrate; a metal layer formed as a metal plate layer or a metal circuit layer; the metal layer being adhered on the adhering layer; and wherein the metal layer is etched to form with metal circuits. Furthermore, electronic elements are adhered on the metal layer to form as circuits. A packaging silicone layer encapsulates the metal layer and the electronic elements for packaging. The circuit board is a flat plate board or a curled board. The silicone are known as polysiloxanes, and are polymer that includes any synthetic compound made up of repeating unit of siloxane, which is a chain of alternating silicon atoms and oxygen atoms, combined with carbon, hydrogen, and sometimes other elements. The silicone is not silicon atoms as those used in wafer.
    Type: Application
    Filed: September 17, 2019
    Publication date: May 21, 2020
    Inventor: WEN YAO CHANG
  • Publication number: 20200070488
    Abstract: A silicon contained integrated structure and the method for forming the same is proposed, wherein a hot melt glue layer is adhered under a silicon layer. The hot melt glue layer contains a high temperature hot melt glue layer and a low temperature hot melt glue layer. By the high temperature hot melt glue layer, the hot melt glue layer may be combined to the silicon layer, while the low temperature hot melt glue layer cause the whole structure can be combined to an object, such as cloth. Furthermore, the present invention uses silicon as material. It can be formed as various specific shapes by molding manufacturing and then the silicon integrated sheet can be transferred to cloth. The whole process is quick and cost is low. Moreover, silicon is not deformed due to heat and thus it has lower effect to the environment than other conventional used material.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventor: WEN YAO CHANG
  • Publication number: 20190270294
    Abstract: A silicon contained integrated structure and the method for forming the same is proposed, wherein a hot melt glue layer is adhered under a silicon layer. The hot melt glue layer contains a high temperature hot melt glue layer and a low temperature hot melt glue layer. By the high temperature hot melt glue layer, the hot melt glue layer may be combined to the silicon layer, while the low temperature hot melt glue layer cause the whole structure can be combined to an object, such as cloth. Furthermore, the present invention uses silicon as material. It can be formed as various specific shapes by molding manufacturing and then the silicon integrated sheet can be transferred to cloth. The whole process is quick and cost is low. Moreover, silicon is not deformed due to heat and thus it has lower effect to the environment than other conventional used material.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Inventor: WEN YAO CHANG
  • Patent number: 10334726
    Abstract: A circuit board with a substrate made of silicon includes a silicon substrate made of silicon; an adhering layer which is a gluing layer and is adhered on the silicon substrate; and a metal layer formed as a metal plate layer or a metal circuit layer; the metal layer being adhered on the adhering layer. Furthermore, the method for forming the circuit board with silicon substrate is proposed, in that a method for forming a circuit board suitable for etching and a method for forming a circuit board for screen printing are proposed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 25, 2019
    Inventor: Wen Yao Chang
  • Publication number: 20190191556
    Abstract: A circuit board with a substrate made of silicon comprises a silicon substrate made of silicon; an adhering layer which is a gluing layer and is adhered on the silicon substrate; a metal layer formed as a metal plate layer or a metal circuit layer; the metal layer being adhered on the adhering layer; and wherein the metal layer is etched to form with metal circuits. Furthermore, electronic elements are adhered on the metal layer to form as circuits with specific functions. A packaging silicon layer encapsulates the metal layer and the electronic elements for packaging. The circuit board is a flat plate board or a curled board.
    Type: Application
    Filed: November 20, 2018
    Publication date: June 20, 2019
    Inventor: WEN YAO CHANG
  • Publication number: 20190191555
    Abstract: A circuit board with a substrate made of silicon includes a silicon substrate made of silicon; an adhering layer which is a gluing layer and is adhered on the silicon substrate; a metal layer formed as a metal plate layer or a metal circuit layer; the metal layer being adhered on the adhering layer; and wherein the metal layer is formed with metal circuits by screen printing. Electronic elements are adhered on the metal layer to form as circuits with specific functions. Materials of the adhering layer contains Organic silicon polyester copolymer resin, Ethyl acetate and Organic silicon resin. Material of the metal layer is selected from copper, aluminum, sliver, and gold. A packaging silicon layer encapsulates the metal layer and the electronic elements for packaging. Material of the metal layer is selected from copper, aluminum, sliver, and gold.
    Type: Application
    Filed: November 12, 2018
    Publication date: June 20, 2019
    Inventor: WEN YAO CHANG
  • Publication number: 20190191554
    Abstract: A circuit board with a substrate made of silicon includes a silicon substrate made of silicon; an adhering layer which is a gluing layer and is adhered on the silicon substrate; and a metal layer formed as a metal plate layer or a metal circuit layer; the metal layer being adhered on the adhering layer. Furthermore, the method for forming the circuit board with silicon substrate is proposed, in that a method for forming a circuit board suitable for etching and a method for forming a circuit board for screen printing are proposed.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventor: WEN YAO CHANG
  • Patent number: 10278283
    Abstract: A circuit board with a substrate made of silicon includes a a silicon substrate made of silicon; an adhering layer which is a gluing layer and is adhered on the silicon substrate; a metal layer formed as a metal plate layer or a metal circuit layer; the metal layer being adhered on the adhering layer. Furthermore, the method for forming the circuit board with silicon substrate is proposed, in that a method for forming a circuit board suitable for etching and a method for forming a circuit board for screen printing are proposed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 30, 2019
    Inventor: Wen Yao Chang
  • Patent number: 10019248
    Abstract: The present invention discloses a system and method for service matching of IM software, which is adapted for operating between a plurality of user devices and a plurality of IM software supplier servers. The IM software supplier server provides at least one IM software associated service. The user device merely installs one of the plurality of IM software, and the user device can access services provided by different IM software supplier servers. The service matching method comprises: relaying a service request to the corresponding IM software supplier server according to a correspondence table defining the IM software and names of the IM software associated service when the user device makes the service request; and returning a feedback of the corresponding IM software supplier server to the user device made the service request.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: July 10, 2018
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Frank Chee-Da Tsai, Wen-Jen Ho, Wen-Yao Chang
  • Publication number: 20180161688
    Abstract: A soft building block assembly includes at least one soft building block element formed by soft material and having at least one buckling portion; by stacking of the soft building block element elements, various kinds of toys being formed; a Shore value of the material of the soft building block element is between 20 to 95. Material of the soft building block element is selected from one of PE(Thermal Plastic Elastomer), TPR(Thermal Plastic Rubber), TPU(Thermal PU, PU(Polyurethane) or thermal static material, such as silica rubber. the soft building block element has at least one of a buckling portion and a coupling portion, and the buckling portion of a soft building block element is buckled to the coupling portion of another soft building block element.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 14, 2018
    Inventor: WEN YAO CHANG
  • Publication number: 20180121184
    Abstract: The present invention discloses a system and method for service matching of IM software, which is adapted for operating between a plurality of user devices and a plurality of IM software supplier servers. The IM software supplier server provides at least one IM software associated service. The user device merely installs one of the plurality of IM software, and the user device can access services provided by different IM software supplier servers. The service matching method comprises: relaying a service request to the corresponding IM software supplier server according to a correspondence table defining the IM software and names of the IM software associated service when the user device makes the service request; and returning a feedback of the corresponding IM software supplier server to the user device made the service request.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 3, 2018
    Inventors: Frank Chee-Da TSAI, Wen-Jen HO, Wen-Yao CHANG
  • Patent number: 9508653
    Abstract: A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kewei Zuo, Wen-Yao Chang, Chien Rhone Wang