Patents by Inventor Wen-Yen Chen

Wen-Yen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107184
    Abstract: A semiconductor device structure and methods of forming the same are described. The method includes forming a fin structure from a substrate, depositing a first semiconductor material on a first semiconductor layer of the fin structure, depositing a second semiconductor material on the first semiconductor material, depositing an interlayer dielectric layer over the second semiconductor material, forming an opening in the interlayer dielectric layer to expose the second semiconductor material, and performing a dopant implantation process to form a doped region. The doped region includes a first portion of the second semiconductor material. Then, the method further includes performing an amorphization process to form an amorphous region, and the amorphous region includes a second portion of the second semiconductor material. The method further includes performing an annealing process to recrystallize the amorphous region.
    Type: Application
    Filed: January 3, 2024
    Publication date: March 27, 2025
    Inventors: Wen-Yen CHEN, Min-Tsang LI, Liang-Yin CHEN, Chi On CHUI, Chia-Cheng CHEN
  • Publication number: 20250089137
    Abstract: A driver circuit for adaptively switching a light-emitting diode current is provided. The driver circuit at least includes a first transistor, a first switching component, a second transistor, a third transistor and an operational amplifier. A first terminal of the first transistor is connected to a first input terminal of the operational amplifier. A first terminal of the first switching component is connected to a control terminal of the first transistor. A control terminal of the second transistor is connected to a second terminal of the first switching component. A first terminal of the third transistor is connected to one or more light-emitting diodes. A second terminal of the third transistor is connected to a first terminal of the second transistor and a second input terminal of the operational amplifier. An output terminal of the operational amplifier is connected to a control terminal of the third transistor.
    Type: Application
    Filed: January 17, 2024
    Publication date: March 13, 2025
    Inventor: WEN-YEN CHEN
  • Publication number: 20240395871
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Patent number: 12154949
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Publication number: 20240379407
    Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240377263
    Abstract: A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Tz-Shian CHEN, Yi-Chao WANG, Wen-Yen CHEN, Li-Ting WANG, Huicheng CHANG, Yee-Chia YEO
  • Publication number: 20240355633
    Abstract: A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventor: Wen-Yen Chen
  • Patent number: 12068168
    Abstract: A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Wen-Yen Chen
  • Patent number: 12002711
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tai-Yen Peng, Wen-Yen Chen, Chih-Hao Chen
  • Patent number: 11955553
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Publication number: 20240088225
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
  • Publication number: 20240079278
    Abstract: A method includes forming a pad layer. The pad layer includes a first portion over a first part of a semiconductor substrate, and a second portion over a second part of the semiconductor substrate. The first portion has a first thickness, and the second portion has a second thickness smaller than the first thickness. The semiconductor substrate is then annealed to form a first oxide layer over the first part of the semiconductor substrate, and a second oxide layer over the second part of the semiconductor substrate. The pad layer, the first oxide layer, and the second oxide layer are removed. A semiconductor layer is epitaxially grown over and contacting the first part and the second part of the semiconductor substrate.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 7, 2024
    Inventors: Jhih-Yong Han, Wen-Yen Chen, Yi-Ting Wu, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230420563
    Abstract: A semiconductor device includes a field effect transistor disposed over a first main surface of a semiconductor substrate, a distributed Bragg reflector disposed over an opposing second main surface of the semiconductor substrate, and a conductive via disposed in the distributed Bragg reflector. The field effect transistor includes a gate structure and a source/drain region. The conductive via passes through the semiconductor substrate and is in direct electrical contact with the source/drain region. A metal silicide is formed in a portion of the source/drain region that is in contact with the conductive via, and thus can reduce contact resistance between the source/drain region and the conductive via. The source/drain region is laser annealed through an opening formed through the distributed Bragg reflector. The distributed Bragg reflector reduces or prevents thermal damage to other regions of the semiconductor device that are protected by the distributed Bragg reflector.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: Wen-Yen CHEN, Tsai-Yu HUANG, Yee-Chia YEO
  • Patent number: 11855146
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
  • Patent number: 11794853
    Abstract: An electric bicycle assistance controlling method and an assistance controlling system are applied to an operation processor of an electric bicycle. The electric bicycle assistance controlling method includes defining several health levels and a first power interval and a second power interval, acquiring one health level and a target heart rate interval, and measuring a current human power and a current heart rate. When the current heart rate is within the target heart rate interval, the operation processor determines the assistance controlling system to output a second motor assistance in response to the current human power inside the first power interval, and determines the assistance controlling system to output a third motor assistance in response to the current human power inside the second power interval.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: October 24, 2023
    Assignee: DARAD INNOVATION CORPORATION
    Inventor: Wen-Yen Chen
  • Publication number: 20230282706
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 7, 2023
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Publication number: 20230260795
    Abstract: A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.
    Type: Application
    Filed: May 24, 2022
    Publication date: August 17, 2023
    Inventor: Wen-Yen Chen
  • Publication number: 20230260804
    Abstract: The method includes performing a well implantation process to dope a dopant into a semiconductor substrate; after performing the well implantation process, performing a flash anneal on the semiconductor substrate, the flash anneal including a first preheat step and a first annealing step after the first preheat step, the first preheat step performed at a preheat temperature ranging from about 200° C. to about 800° C., the first annealing step having a peak temperature ramp profile, the peak temperature ramp profile having a peak temperature ranging from about 1000° C. to about 1200° C.; after performing the flash anneal, performing a rapid thermal anneal (RTA) on the semiconductor substrate, the RTA including a second preheat step, the first preheat step of the flash anneal being performed for a shorter duration than the second preheat step of the RTA.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhih-Yong HAN, Wen-Yen CHEN, Po-Kang HO, Tsai-Yu HUANG, Huicheng CHANG, Yee-Chia YEO
  • Publication number: 20230215758
    Abstract: A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Wen-Yen Chen, Li-Ting Wang, Wan-Chen Hsieh, Bo-Cyuan Lu, Tai-Chun Huang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11695042
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang