Patents by Inventor Wen-Yi Hsu

Wen-Yi Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10807328
    Abstract: A method to make dyed functional film comprising the steps of providing a soluble polymer material; adding an appropriate solvent to the polymer material to make a soluble polymer solution; providing a soluble dye; adding an appropriate solvent to the dye to make a soluble dye solution; adding the dye solution to the polymer or PVA solution, and introducing the dyed polymer or PVA solution to a solution casting device; removing a thin dyed functional film from the casting device; and letting the dyed functional film dry and solidified.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: October 20, 2020
    Inventor: Roger Wen Yi Hsu
  • Patent number: 10802243
    Abstract: A lens assembly driving module includes a holder, a metal yoke, a lens unit, a magnet set, a coil, at least one elastic element and at least one damper agent. The metal yoke is coupled with the holder and includes a through hole and at least one extending structure. The extending structure is disposed around the through hole and extends along a direction from the through hole to the holder. The lens unit is movably disposed in the metal yoke. The lens unit includes an optical axis and at least one notch structure. The notch structure is disposed in an outer peripheral area of the lens unit and is corresponding to the extending structure. The damper agent is disposed between the extending structure of the metal yoke and the notch structure of the lens unit. The damper agent is applied to damp a movement of the lens unit.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 13, 2020
    Assignee: LARGAN DIGITAL CO., LTD.
    Inventors: Chun-Yi Lu, Te-Sheng Tseng, Wen-Hung Hsu, Ming-Ta Chou
  • Patent number: 10763446
    Abstract: An organic thin film transistor includes a substrate, a source/drain layer that is located on the substrate and has a source region and a drain region, a first buffer layer that is located between the source region and the drain region, a semiconductor layer that is located on the source/drain layer and the first buffer layer, a gate insulating layer, and a gate electrode. The first buffer layer covers at least one portion of the source region and at least one portion of the drain region. The first buffer layer is located among the semiconductor layer, the source region, the drain region, and the substrate. The gate insulating layer covers the source/drain layer and the semiconductor layer. The gate electrode is located on the gate insulating layer, and a portion of the gate insulating layer is located between the gate electrode and the semiconductor layer.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 1, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Kuan-Yi Lin, Wen-Chung Tang, Po-Wei Chen, Yu-Lin Hsu
  • Patent number: 10763836
    Abstract: Disclosed is a measuring circuit for quantizing variations in the operating speed of a target circuit. The measuring circuit includes: a signal generator configured to generate a predetermined signal; an adjustable delay circuit configured to generate a first and second delay signals according to the predetermined signal respectively; a signal detector configured to detect the first and second delay signals respectively and thereby generate a first and second detection results respectively; and a calibrating circuit configured to enable a first and second numbers of delay units of the adjustable delay circuit according to the first and second detection results respectively so as to make each of the delays respectively caused by the first and second numbers of delay units be less than a delay threshold, in which the first and second numbers relate to the operating speed of the target circuit operating in the first and second conditions respectively.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 1, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Yi Kuo, Ying-Yen Chen, Wen-Hsuan Hsu
  • Publication number: 20200271945
    Abstract: A lens driving module includes a holder, a cover, a carrier, at least one first magnet, a first coil, at least two second magnets, at least one first sensor and at least one second sensor. The holder includes an opening hole. The cover is made of metal material and coupled to the holder. The carrier is movably disposed in the cover and for coupling to a lens. The first magnet is movably disposed in the cover. The first coil is wound around an outer side of the carrier. The second magnets are disposed on one end of the carrier. The first sensor is for detecting a magnetic field of the second magnets. The second sensor is for detecting a magnetic field of the first magnet.
    Type: Application
    Filed: May 13, 2020
    Publication date: August 27, 2020
    Inventors: Chun-Yi LU, Te-Sheng TSENG, Wen-Hung HSU
  • Publication number: 20200225793
    Abstract: A touch display panel is provided, including a common electrode ring, a first and a second common electrode pattern, pixel structures, an edge common signal line, and common signal lines disposed on a substrate. The first and second common electrode patterns and the pixel structures are located in a region surrounded by the common electrode ring. The first common electrode pattern is spaced from the second common electrode pattern by a gap. The first and the second common electrode patterns respectively overlap some of the pixel structures. The edge common signal line is disposed on the substrate, traces along the gap, and extends toward the common electrode ring to be electrically connected to the common electrode ring. The first common electrode pattern overlaps and is electrically connected to one common signal line. The second common electrode pattern overlaps and is electrically connected to another common signal line.
    Type: Application
    Filed: October 8, 2019
    Publication date: July 16, 2020
    Applicant: Au Optronics Corporation
    Inventors: Te-Chun Huang, Wen-Yi Hsu, Zeng-De Chen, Pei-Ming Chen
  • Publication number: 20200212901
    Abstract: Disclosed is a measuring circuit for quantizing variations in the operating speed of a target circuit. The measuring circuit includes: a signal generator configured to generate a predetermined signal; an adjustable delay circuit configured to generate a first and second delay signals according to the predetermined signal respectively; a signal detector configured to detect the first and second delay signals respectively and thereby generate a first and second detection results respectively; and a calibrating circuit configured to enable a first and second numbers of delay units of the adjustable delay circuit according to the first and second detection results respectively so as to make each of the delays respectively caused by the first and second numbers of delay units be less than a delay threshold, in which the first and second numbers relate to the operating speed of the target circuit operating in the first and second conditions respectively.
    Type: Application
    Filed: September 27, 2019
    Publication date: July 2, 2020
    Inventors: CHUN-YI KUO, YING-YEN CHEN, WEN-HSUAN HSU
  • Publication number: 20200212900
    Abstract: Disclosed is a circuit operating speed detecting circuit configured to detect an operating speed of a target circuit during a monitor mode. The circuit operating speed detecting circuit includes a signal generator, an adjustable delay circuit, and a signal detector. During the monitor mode, the signal generator generates a predetermined signal in a current operating condition, the adjustable delay circuit generates a delay signal according to the predetermined signal in the current operating condition, and the signal detector detects the degree of delay of the delay signal in the current operating condition so as to generate a first result if the degree of delay is not greater than a predetermined threshold and generate a second result if the degree of delay is greater than the predetermined threshold, in which the first and the second results are related to the operating speed of the target circuit.
    Type: Application
    Filed: September 17, 2019
    Publication date: July 2, 2020
    Inventors: CHUN-YI KUO, WEN-HSUAN HSU, YING-YEN CHEN
  • Patent number: 10690935
    Abstract: A lens driving module includes a holder, a cover, a carrier, at least one first magnet, a first coil, at least two second magnets, at least one first sensor and at least one second sensor. The holder includes an opening hole. The cover is made of metal material and coupled to the holder. The carrier is movably disposed in the cover and for coupling to a lens. The first magnet is movably disposed in the cover. The first coil is wound around an outer side of the carrier. The second magnets are disposed on one end of the carrier. The first sensor is for detecting a magnetic field of the second magnets. The second sensor is for detecting a magnetic field of the first magnet.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 23, 2020
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chun-Yi Lu, Te-Sheng Tseng, Wen-Hung Hsu
  • Patent number: 10686433
    Abstract: Disclosed is a circuit operating speed detecting circuit configured to detect an operating speed of a target circuit during a monitor mode. The circuit operating speed detecting circuit includes a signal generator, an adjustable delay circuit, and a signal detector. During the monitor mode, the signal generator generates a predetermined signal in a current operating condition, the adjustable delay circuit generates a delay signal according to the predetermined signal in the current operating condition, and the signal detector detects the degree of delay of the delay signal in the current operating condition so as to generate a first result if the degree of delay is not greater than a predetermined threshold and generate a second result if the degree of delay is greater than the predetermined threshold, in which the first and the second results are related to the operating speed of the target circuit.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: June 16, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-yi Kuo, Wen-Hsuan Hsu, Ying-Yen Chen
  • Publication number: 20200135664
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Publication number: 20200135891
    Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 30, 2020
    Inventors: Cheng-Yi PENG, Wen-Yuan CHEN, Wen-Hsing HSIEH, Yi-Ju HSU, Jon-Hsu HO, Song-Bor LEE, Bor-Zen TIEN
  • Publication number: 20200124821
    Abstract: A lens driving apparatus includes a holder, a cover, a carrier, a first magnet, a coil, a spring, two second magnets and a hall sensor. The holder includes an opening hole. The cover is made of metal material and coupled to the holder. The carrier is movably disposed in the cover, and for coupling to a lens. The first magnet is connected to an inner side of the cover. The coil is wound around an outer side of the carrier, and adjacent to the first magnet. The spring is coupled to the carrier. The second magnets are disposed on one end of the carrier which is toward the holder. The hall sensor is for detecting a magnetic field of any one of the second magnets, wherein the magnetic field is varied according to a relative displacement between the hall sensor and the second magnet which is detected.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Chun-Yi LU, Te-Sheng TSENG, Wen-Hung HSU
  • Publication number: 20200117848
    Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Chung-Yun CHENG, Chin-Chang HSU, Hsien-Hsin Sean LEE, Jian-Yi LI, Li-Sheng KE, Wen-Ju YANG
  • Patent number: 10616542
    Abstract: A multi-dimensional image projection apparatus is provided. The multi-dimensional image projection apparatus includes an image projector and an image-processing circuit. The image-processing circuit is configured to receive an input image, and perform a linearity transformation process and a first inverse image warping process on the input image according to sensor information about the multi-dimensional image projection apparatus relative to the projection surface to generate a first image. The image-processing circuit performs a matrix transformation process and a second inverse image warping process on the first image according to the sensor information to generate a second image, and generate an output image according to the second image. The image projector projects the output image onto the projection surface.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: April 7, 2020
    Assignee: Terawins, Inc.
    Inventors: Yu Kuang Wang, Wen Yi Huang, Pei Kai Hsu, Wei Ya Wu
  • Patent number: 10611106
    Abstract: A method to make dyed functional film comprising the steps of providing a soluble polymer material; adding an appropriate solvent to the polymer material to make a soluble polymer solution; providing a soluble dye; adding an appropriate solvent to the dye to make a soluble dye solution; adding the dye solution to the polymer or PVA solution, and introducing the dyed polymer or PVA solution to a solution casting device; removing a thin dyed functional film from the casting device; and letting the dyed functional film dry and solidified.
    Type: Grant
    Filed: October 18, 2015
    Date of Patent: April 7, 2020
    Inventor: Roger Wen Yi Hsu
  • Publication number: 20200105857
    Abstract: An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, first and second scan lines, a data line, first and second active devices and first and second pixel electrodes. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is electrically connected to the first scan line. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to same layer. The second gate is electrically connected to the second scan line. The second pixel electrode is electrically connected to the second drain.
    Type: Application
    Filed: August 19, 2019
    Publication date: April 2, 2020
    Applicant: Au Optronics Corporation
    Inventors: Ming-Yao Chen, Kuo-Yu Huang, Wen-Yi Hsu
  • Publication number: 20200094298
    Abstract: A method includes introducing ozone toward a photoresist layer over a substrate. The ozone is decomposed into dioxygen and first atomic oxygen. The dioxygen is decomposed into second atomic oxygen. The first atomic oxygen and the second atomic oxygen are reacted with the photoresist layer. An apparatus that performs the method is also disclosed.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Chuan CHANG, Shao-Yen KU, Wen-Chang TSAI, Shang-Yuan YU, Chien-Wen HSIAO, Fan-Yi HSU
  • Patent number: 10600812
    Abstract: A manufacturing method of an array substrate including following steps is provided. A plurality of scan lines are formed on a substrate having a pixel region and a fan-out region. A plurality of data lines are formed. A plurality of transistors are formed and respectively electrically connected to the corresponding scan lines and data lines. A plurality of common electrodes are formed. A plurality of pixel electrodes are formed and respectively electrically connected to the corresponding transistors. A plurality of first fan-out lines, second fan-out lines, and third fan-out lines are formed in the fan-out region. Each of the third fan-out lines includes a transparent conductive layer and an auxiliary conductive layer located on and contacting the transparent conductive layer. The third fan-out lines and the common electrodes are formed by the same photomask.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: March 24, 2020
    Assignee: Au Optronics Corporation
    Inventors: Wen-Yi Hsu, Pei-Ming Chen, Maw-Song Chen
  • Patent number: D882258
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 28, 2020
    Inventor: Roger Wen Yi Hsu