Abstract: A connection assembly, which is suitable to connect a first body of a portable electronic apparatus with a second body thereof, is provided. The connection assembly includes a positioning unit, first electrical connectors and a second electrical connector. The positioning unit is rotatably connected to the first body and removably connected to the second body. The first electrical connectors are connected to the positioning unit, and the second electrical connector is connected to the second body so as to connect to one of the first electrical connectors. Therefore, the connection assembly occupies only a little area of surfaces of the two bodies.

Abstract: A base suitable for a portable electronic apparatus is provided. The portable electronic apparatus includes a first body which has a first electrical connector. The base includes a second body, a supporting member, and a second electrical connector. The supporting member has a first end and a second end opposite to the first end. The first end is pivotally connected to the second body along a first rotation axis. The second electrical connector for connecting with the first electrical connector is pivotally connected to the second end along a second rotation axis. In addition, the second body has a recess for accommodating the supporting member and the second electrical connector after rotation. A portable electronic apparatus which has the base is also provided.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. “Horizontal synchronization vibration” and “Remapping” are the two methods of the present invention.

Abstract: A rotatable camera has a lens unit comprising a photographing head and an oblique driving shaft arranged in oblique position with the photographing head, a bearing support for pivotally mounting the photographing head inside, a motor and a driving gear set driven by the motor to in turn drive the oblique driving shaft to generate rotating motion, when the oblique shaft is in rotating motion, the photographing head of the lens unit immediately rotates and changes the angle of photographing so that the rotatable camera employs only a single motor to drive the photographing head of the lens unit to rapidly move to the direction to be monitored, particularly, due to no time delay any corners shall be monitored by the rotatable camera.

Abstract: A connection assembly, which is suitable to connect a first body of a portable electronic apparatus with a second body thereof, is provided. The connection assembly includes a positioning unit, first electrical connectors and a second electrical connector. The positioning unit is rotatably connected to the first body and removably connected to the second body. The first electrical connectors are connected to the positioning unit, and the second electrical connector is connected to the second body so as to connect to one of the first electrical connectors. Therefore, the connection assembly occupies only a little area of surfaces of the two bodies.

Abstract: A base suitable for a portable electronic apparatus is provided. The portable electronic apparatus includes a first body which has a first electrical connector. The base includes a second body, a supporting member, and a second electrical connector. The supporting member has a first end and a second end opposite to the first end. The first end is pivotally connected to the second body along a first rotation axis. The second electrical connector for connecting with the first electrical connector is pivotally connected to the second end along a second rotation axis. In addition, the second body has a recess for accommodating the supporting member and the second electrical connector after rotation. A portable electronic apparatus which has the base is also provided.

Abstract: A panel assembly structure including a first connecting portion, a first screw, a second connecting portion and a second screw for fixing a display panel on a panel cover is provided. The first connecting portion having a first connecting through hole is formed on the cover and extends toward a first side of the panel. The first screw is screwed into the first connecting through hole and a first panel threaded hole on the first side for fastening the first connecting portion and the first side. The second connecting portion having a second connecting through hole is formed on the inner surface of the cover and extends toward a second side of the panel. The second screw is screwed into the second connecting through hole and a second panel threaded hole on the second side of the panel for fastening the second connecting portion and the second side.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The present invention is to provide a method for designing a video and image scaler based on 2-D Finite Impulse Response (FIR) filter. First, a 2-D video/image source is sampled with sampling rate higher than Nyquist rate to obtain 2-D samples; second, zeros are padded in between the 2-D samples to get a zero padding image; third, the zero padding image is passed through a 2-D FIR filter and a scaled-up image is obtained.

Abstract: A fault-tolerant computer system includes first and second central processing units (CPUs) producing essentially identical data output streams, a voter delay buffer having a first FIFO buffer and a second FIFO buffer, and an I/O module connected to the CPUs. The I/O module includes a comparator for bitwise comparing the CPU data output streams. The first CPU data output stream is transmitted to peripheral devices if both CPU outputs remain substantially identical. Otherwise, if the comparator indicates differences, queued first and second CPU data are routed to the first and second FIFOs respectively, and subsequent data are retained in respective CPU buffers. While the CPUs continue processing, ongoing diagnostic procedures attempt to identify one or the other of the CPUs as malfunctioning and the remaining CPU as correctly-functioning. If the resulting diagnosis is inconclusive, the CPU having the lower rate of error correction is identified as being correctly-functioning.

Abstract: A network adapter for interfacing between a communication network and a host computer operating as a network device, and a method of operation of these components. The adapter is initially conditioned to transmit at a lower of two possible speeds, such as 10 Mbps instead of 100 Mbps, and then senses at which speed the network is operating, before matching to this sensed speed, either the higher speed or the lower speed. If the sensed speed is the lower speed, the adapter transmits a burst of high-speed signals and senses again for high-speed operation. If the network has not switched to high-speed operation, the adapter is conditioned for low-speed operation. After the adapter is conditioned for low-speed or high-speed operation, the network speed is continually sensed and, if the network is not operating at the selected speed for some preselected period of time, the adapter is returned to its initial low-speed state to begin network speed sensing over again.