Patents by Inventor Wen-Yi Wong

Wen-Yi Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10121848
    Abstract: A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.
    Type: Grant
    Filed: May 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Powerchip Technology Corporation
    Inventors: Shyng-Yeuan Che, Wen-Yi Wong
  • Publication number: 20170250245
    Abstract: A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.
    Type: Application
    Filed: May 14, 2017
    Publication date: August 31, 2017
    Inventors: Shyng-Yeuan Che, Wen-Yi Wong
  • Patent number: 9735228
    Abstract: A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.
    Type: Grant
    Filed: January 3, 2016
    Date of Patent: August 15, 2017
    Assignee: Powerchip Technology Corporation
    Inventors: Shyng-Yeuan Che, Wen-Yi Wong
  • Publication number: 20170069710
    Abstract: A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.
    Type: Application
    Filed: January 3, 2016
    Publication date: March 9, 2017
    Inventors: Shyng-Yeuan Che, Wen-Yi Wong
  • Publication number: 20150371862
    Abstract: A method of forming a pattern including following steps is provided. A wafer is provided, wherein the wafer includes a plurality of wafer interior dies and a plurality of wafer edge dies. A first pattern is formed on each of the wafer interior dies, and a second pattern is formed on each of the wafer edge dies. A method of forming the first patterns includes performing at least two exposure processes, and a method of forming the second patterns includes performing at least one of the at least two exposure processes, wherein a number of the exposure processes performed for forming the second patterns is less than a number of the exposure processes performed for forming the first patterns.
    Type: Application
    Filed: September 26, 2014
    Publication date: December 24, 2015
    Inventors: Wen-Yi Wong, Tuz-Wen Weng