Abstract: An RF testing method is applied between a testing instrument and multiple devices under test at least including a first DUT and a second DUT. The testing instrument includes a signal generator and a signal analyzer. A sync signal is sent to the testing instrument and the first DUT, so that the first DUT occupies the signal generator to receive a testing signal from the signal generator. The first DUT sends an uplink signal to the signal analyzer based on the testing signal to occupy the signal analyzer for signal analysis at a first point in time. The sync signal is sent to the testing instrument and the second DUT, so that the second DUT occupies the signal generator to receive the testing signal from the signal generator at a second point in time. The first point in time is parallel to the second point in time.

Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.

Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.

Abstract: A method for extracting flavone aglycones in Chrysanthemum morifolium is provided. The method includes: (a) immersing a Chrysanthemum morifolium raw material in water or an aqueous solution to perform an immersion procedure for 3.5 hours or more to obtain an immersion sample; and (b) adding an extraction solvent to the immersion sample to perform an extraction procedure 5-60 minutes to obtain an extract. The Chrysanthemum morifolium raw material includes at least one of the following parts of Chrysanthemum morifolium: whole plant, roots, stems, leaves and flowers.

Abstract: A method for producing galanthamine using a plant, includes (a) performing a thermal treatment on a living plant to induce accumulation of galanthamine therein, wherein the living plant is a plant belonging to the family Amaryllidaceae; and (b) placing the living plant in a medium and performing an electrical stimulation treatment on the living plant to release the galanthamine from the living plant to the medium.

Abstract: A method for inducing plants to increase their flavonoid compound content, includes performing an induction culture on a young shoot or an adult of a living plant, wherein flavonoid compound content of the young shoot or the adult of the living plant which has been subjected to the induction culture is higher than that of a young shoot or an adult of a living plant which is not subjected to the induction culture. Moreover, the induction culture includes a metal ion stimulation procedure comprising culturing the young shoot or the adult of the living plant in a culture environment with metal ion stimulation, wherein the culture environment with metal ion stimulation contains a metal ion used for stimulating the living plant, and the concentration of the metal ion used for stimulating the living plant is 5 ?M-50 mM.

Abstract: A method for inducing plants to increase their flavonoid compound content, includes performing an induction culture on a young shoot or an adult of a living plant, wherein flavonoid compound content of the young shoot or the adult of the living plant which has been subjected to the induction culture is higher than that of a young shoot or an adult of a living plant which is not subjected to the induction culture. Moreover, the induction culture includes a metal ion stimulation procedure comprising culturing the young shoot or the adult of the living plant in a culture environment with metal ion stimulation, wherein the culture environment with metal ion stimulation contains a metal ion used for stimulating the living plant, and the concentration of the metal ion used for stimulating the living plant is 5 ?M-50 mM.

Abstract: A method for producing galanthamine using a plant, includes (a) performing a thermal treatment on a living plant to induce accumulation of galanthamine therein, wherein the living plant is a plant belonging to the family Amaryllidaceae; and (b) placing the living plant in a medium and performing an electrical stimulation treatment on the living plant to release the galanthamine from the living plant to the medium.