Abstract: A semiconductor device includes a metal-insulator-semiconductor high-electron-mobility transistor (MISHEMT) and a Schottky gate HEMT. The Schottky gate HEMT and the MISHEMT are connected in series, and a Schottky gate of the Schottky gate HEMT is electrically connected with the source of the MISHEMT so as to generate a forward diode from the source to the drain of the MISHEMT. The series-connected structure is good for increasing the breakdown voltage of the semiconductor device, and the forward diode can reduce the power loss.

Abstract: A high electron mobility transistor (HEMT) device and a manufacturing method thereof are provided. The HEMT device includes a channel layer, a barrier layer, a first gate electrode, a first drain electrode and a first source electrode. The channel layer is disposed on a substrate. A surface of a portion of the channel layer within a first region of the HEMT device includes a polar plane and a non-polar plane. The barrier layer is conformally disposed on the channel layer. The first gate electrode is disposed on the barrier layer, and located within the first region. The first drain electrode and the first source electrode are disposed within the first region, and located at opposite sides of the first gate electrode.

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a first channel layer, a second channel layer, a cap layer, a first metal nitride layer, a gate, a source, and a drain is provided. The first channel layer is disposed on the substrate. The second channel layer is disposed on the first channel layer. The cap layer is disposed on the second channel layer and exposes a portion of the second channel layer. The first metal nitride layer is disposed on the cap layer. The gate is disposed on the first metal nitride layer. The width of the first metal nitride layer is greater than or equal to the width of the gate. The source and the drain are disposed on the second channel layer at two sides of the gate.

Abstract: A high electron mobility transistor (HEMT) device and a manufacturing method thereof are provided. The HEMT device includes a channel layer, a barrier layer, a first gate electrode, a first drain electrode and a first source electrode. The channel layer is disposed on a substrate. A surface of a portion of the channel layer within a first region of the HEMT device includes a polar plane and a non-polar plane. The barrier layer is conformally disposed on the channel layer. The first gate electrode is disposed on the barrier layer, and located within the first region. The first drain electrode and the first source electrode are disposed within the first region, and located at opposite sides of the first gate electrode.

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a first channel layer, a second channel layer, a cap layer, a first metal nitride layer, a gate, a source, and a drain is provided. The first channel layer is disposed on the substrate. The second channel layer is disposed on the first channel layer. The cap layer is disposed on the second channel layer and exposes a portion of the second channel layer. The first metal nitride layer is disposed on the cap layer. The gate is disposed on the first metal nitride layer. The width of the first metal nitride layer is greater than or equal to the width of the gate. The source and the drain are disposed on the second channel layer at two sides of the gate.

Abstract: A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

Abstract: A semiconductor apparatus includes a high side region and a low side region, wherein the high side region includes semiconductor devices, and those semiconductor devices have at least two devices with different operating voltages. In the high side region, at least one isolation structure is located between the devices with different operating voltages to prevent short circuit between the devices.

Abstract: Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction transistor (BJT), and a first well region having the P-type conductivity. The buried layer is located on the substrate. The NPN BJT is located on the buried layer. The first well region is located between the buried layer and the NPN BJT. The NPN BJT is separated from the buried layer by the first well region.

Abstract: A semiconductor device including a substrate, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a plurality of junction gate field-effect transistors (JFETs) connected in parallel is provided. The MOSFET is disposed on a substrate. The MOSFET includes a source region, a drain region, and a gate structure disposed between the source region and the drain region. The JFETs and the MOSFET are connected in series. Each of the JFETs laterally extends between the source region and the drain region.

Abstract: A semiconductor device including a substrate of a first conductivity type, a metal-oxide-semiconductor-field-effect transistor (MOSFET), junction gate field-effect transistors (JFETs), an isolation structure, and a buried layer of a second conductivity type is provided. The MOSFET is located on the substrate and has a first epitaxial layer of the second conductivity type. The JFET is located on the substrate and has a second epitaxial layer of the second conductivity type. The isolation structure is located between the MOSFET and the JFET to separate the first epitaxial layer from the second epitaxial layer. The buried layer is located between the MOSFET and the substrate. The buried layer extends from below the MOSFET to below the isolation structure and below the JFET, so as to electrically connect the MOSFET to the first JFET.

Abstract: A semiconductor apparatus includes a high side region and a low side region, wherein the high side region includes semiconductor devices, and those semiconductor devices have at least two devices with different operating voltages. In the high side region, at least one isolation structure is located between the devices with different operating voltages to prevent short circuit between the devices.

Abstract: A semiconductor device including a substrate of a first conductivity type, a metal-oxide-semiconductor-field-effect transistor (MOSFET), junction gate field-effect transistors (JFETs), an isolation structure, and a buried layer of a second conductivity type is provided. The MOSFET is located on the substrate and has a first epitaxial layer of the second conductivity type. The JFET is located on the substrate and has a second epitaxial layer of the second conductivity type. The isolation structure is located between the MOSFET and the JFET to separate the first epitaxial layer from the second epitaxial layer. The buried layer is located between the MOSFET and the substrate. The buried layer extends from below the MOSFET to below the isolation structure and below the JFET, so as to electrically connect the MOSFET to the first JFET.

Abstract: A semiconductor device including a substrate, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a plurality of junction gate field-effect transistors (JFETs) connected in parallel is provided. The MOSFET is disposed on a substrate. The MOSFET includes a source region, a drain region, and a gate structure disposed between the source region and the drain region. The JFETs and the MOSFET are connected in series. Each of the JFETs laterally extends between the source region and the drain region.

Abstract: A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

Abstract: Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction transistor (BJT), and a first well region having the P-type conductivity. The buried layer is located on the substrate. The NPN BJT is located on the buried layer. The first well region is located between the buried layer and the NPN BJT. The NPN BJT is separated from the buried layer by the first well region.

Abstract: A method includes forming a first nitride layer on a semiconductor substrate, forming a first oxide layer on the first nitride layer, forming a first trench through the first oxide layer, the first nitride layer and a portion of the semiconductor substrate, forming a first spacer on a sidewall of the first trench, forming a second trench in the semiconductor substrate by using the first spacer as a mask, forming a third trench, forming a second oxide layer in the second trench, wherein the second oxide layer laterally extends into the semiconductor substrate and under the first spacer, forming a second spacer on a sidewall of the third trench, and removing a portion of the first nitride layer and a portion of the semiconductor substrate by etching and using the second spacer as a mask to form a fin structure on the second oxide layer.

Abstract: A reference voltage generating circuit. A bandgap circuit includes a current mirror circuit and an output circuit. The current mirror circuit generates a first current. The output circuit generates a reference current based on the first current. A compensation circuit is coupled to the bandgap circuit in parallel at a combination node and generates a compensation current. The compensation current is smaller than the reference current. The reference current has a first temperature coefficient and the compensation current has a second temperature coefficient that is inverse to the first temperature coefficient. The reference current and the compensation current are combined at the combination node, such that an absolute value of a temperature coefficient of the reference voltage of the combination node is smaller than an absolute value of the first temperature coefficient and an absolute value of the second temperature coefficient.

Abstract: A reference voltage generating circuit. A bandgap circuit includes a current mirror circuit and an output circuit. The current mirror circuit generates a first current. The output circuit generates a reference current based on the first current. A compensation circuit is coupled to the bandgap circuit in parallel at a combination node and generates a compensation current. The compensation current is smaller than the reference current. The reference current has a first temperature coefficient and the compensation current has a second temperature coefficient that is inverse to the first temperature coefficient. The reference current and the compensation current are combined at the combination node, such that an absolute value of a temperature coefficient of the reference voltage of the combination node is smaller than an absolute value of the first temperature coefficient and an absolute value of the second temperature coefficient.

Abstract: A nonvolatile memory cell array is formed by arranging a plurality of storage memory cells in array. A plurality of bit lines are used to electrically connect memory cells on transversal rows. A plurality of word lines are used to electrically connect memory cells on longitudinal columns. The combination of each word line and each bit line represents a specific storage memory cell. The source of the transistor in each storage memory cell is electrically connected to a corresponding word line, while the gate and drain thereof are electrically together connected to a corresponding bit line. Therefore, the area of memory cell can be effectively shrunk, and the integration density of memory cell can also be effectively enhanced.

Abstract: The present invention generally relates to provide a fabrication method for forming a flash memory device provided with an adjustable sharp end structure of the floating gate. While the present invention utilizes the dielectric spacer to form the L-shaped floating gate provided with a sharp end structure, the present invention adjust the thickness of the polysilicon layer and the dielectric layer covering on the polysilicon layer surface to adjust the position of the dielectric spacer so as to change the position of the sharp end structure of the L-shaped floating gate and to enhance the ability of erasing control of the flash memory and to simultaneously form a stable and easily controlled channel length and the sharp end structure for point discharging.